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Add test for OPX+ and Octave.
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deanpoulos committed Nov 7, 2024
1 parent ba4d8f5 commit 0d73600
Showing 1 changed file with 51 additions and 1 deletion.
52 changes: 51 additions & 1 deletion tests/wirer/test_wirer_cross_resonance.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@
from qualang_tools.wirer import *
from qualang_tools.wirer.connectivity.element import QubitPairReference, QubitReference
from qualang_tools.wirer.connectivity.wiring_spec import WiringLineType
from qualang_tools.wirer.instruments.instrument_channel import InstrumentChannelMwFemOutput
from qualang_tools.wirer.instruments.instrument_channel import InstrumentChannelMwFemOutput, InstrumentChannelOpxPlus, \
InstrumentChannelOpxPlusOutput, InstrumentChannelOctaveOutput

visualize_flag = False

Expand Down Expand Up @@ -47,3 +48,52 @@ def test_2q_allocation_cross_resonance(instruments_2lf_2mw):
InstrumentChannelMwFemOutput(con=1, port=3, slot=3)
][i]
)


def test_2q_allocation_cross_resonance_opx_plus_octave(instruments_1opx_1octave):
qubits = [1, 2]
qubit_pairs = [(1, 2), (2, 1)]

connectivity = Connectivity()

connectivity.add_resonator_line(qubits=qubits)
allocate_wiring(connectivity, instruments_1opx_1octave)

connectivity.add_qubit_drive_lines(qubits=qubits)
allocate_wiring(connectivity, instruments_1opx_1octave, block_used_channels=False)

connectivity.add_qubit_pair_zz_drive_lines(qubit_pairs)
allocate_wiring(connectivity, instruments_1opx_1octave, block_used_channels=False)

connectivity.add_qubit_pair_cross_resonance_lines(qubit_pairs)
allocate_wiring(connectivity, instruments_1opx_1octave)

if visualize_flag:
visualize(connectivity.elements, instruments_1opx_1octave.available_channels)


for i, qubit_pair in enumerate(qubit_pairs):
xy_channels = connectivity.elements[QubitReference(qubit_pair[0])].channels[WiringLineType.DRIVE]
cr_channels = connectivity.elements[QubitPairReference(*qubit_pair)].channels[WiringLineType.CROSS_RESONANCE]
zz_channels = connectivity.elements[QubitPairReference(*qubit_pair)].channels[WiringLineType.ZZ_DRIVE]
assert len(xy_channels) == 3
assert len(cr_channels) == 3
assert len(zz_channels) == 3

# For each XY, XD and ZZ should be on the same channel for the same qubit pair + control index
for channels in [xy_channels, cr_channels, zz_channels]:
for j, channel in enumerate(channels):
assert pytest.channels_are_equal(
channel, [
[
InstrumentChannelOpxPlusOutput(con=1, port=3),
InstrumentChannelOpxPlusOutput(con=1, port=4),
InstrumentChannelOctaveOutput(con=1, port=2),
],
[
InstrumentChannelOpxPlusOutput(con=1, port=5),
InstrumentChannelOpxPlusOutput(con=1, port=6),
InstrumentChannelOctaveOutput(con=1, port=3),
],
][i][j]
)

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