Specified top module for Verilator

rejunity · Oct 26, 2024 · 0918e86 · 0918e86
1 parent 71c3cb1
commit 0918e86
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/src/tt_um_rejunity_atari2600.v b/src/tt_um_rejunity_atari2600.v
@@ -651,8 +651,8 @@ module tt_um_rejunity_atari2600 (
   wire  [7:0] spi_data_read;
   reg         spi_data_ready;
   wire        spi_busy;
-  qspi_flash_controller #(.DATA_WIDTH_BYTES(1), .ADDR_BITS(24)) flash_rom (
   `ifdef QSPI_ROM
+  qspi_flash_controller #(.DATA_WIDTH_BYTES(1), .ADDR_BITS(24)) flash_rom (
     .clk(clk),
     .rstn(rst_n),
 
@@ -672,7 +672,7 @@ module tt_um_rejunity_atari2600 (
     .data_out(spi_data_read),
     .data_ready(spi_data_ready),
     .busy(spi_busy)
-  `endif
   );
+  `endif
 
 endmodule
diff --git a/verilator/Makefile b/verilator/Makefile
@@ -18,7 +18,7 @@ a2600: V${TOP}.mk
 
 V${TOP}.mk: ${MAIN_CPP}
 	verilator ${VFLAGS} ${WFLAGS} -I${SRC_DIR} \
-		-cc  ${TOP}.v ${PROJECT_SOURCES}  --exe $< -o ${EXEC_NAME} \
+		-top $(TOP) -cc  ${TOP}.v ${PROJECT_SOURCES}  --exe $< -o ${EXEC_NAME} \
 		-CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}"
 
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