TEST: introduced NO_ROM_MACROS define

rejunity · Nov 10, 2024 · 6cd516c · 6cd516c
1 parent e84618d
commit 6cd516c
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Showing 4 changed files with 8 additions and 14 deletions.
diff --git a/fpga/icebreaker.v b/fpga/icebreaker.v
@@ -12,6 +12,7 @@
 
 // `define VGA_50MHz
 // `define QSPI_ROM_EMU
+`define NO_MACRO_ROMS
 `define QSPI_ROM
 
 module vga_pll(

diff --git a/src/tt_um_rejunity_atari2600.v b/src/tt_um_rejunity_atari2600.v
@@ -311,17 +311,7 @@ module tt_um_rejunity_atari2600 (
   reg  [7:0] rom2_data_r;
   reg  [7:0] rom3_data_r;
 
-`ifdef SIM
-  always @(*)
-   casez ({use_internal_rom, rom_config[3:1]})
-     4'b0zzz: rom_data = external_rom_data;
-     4'b10zz: rom_data = internal_rom_data;
-     4'b1100: rom_data = internal_rom_data;
-     4'b1101: rom_data = internal_rom_data;
-     4'b1110: rom_data = internal_rom_data;
-     4'b1111: rom_data = internal_rom_data;
-   endcase
-`elsif FPGA
+`ifdef NO_MACRO_ROMS
   always @(*)
    casez ({use_internal_rom, rom_config[3:1]})
      4'b0zzz: rom_data = external_rom_data;

diff --git a/test/Makefile b/test/Makefile
@@ -12,14 +12,16 @@ PROJECT_SOURCES += palette_24bpp.v
 ifneq ($(GATES),yes)
 
 # RTL simulation:
-SIM_BUILD				= sim_build/rtl
+SIM_BUILD        = sim_build/rtl
+COMPILE_ARGS    += -DNO_MACRO_ROMS
+COMPILE_ARGS    += -DSIM
 VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES))
-COMPILE_ARGS 		+= -I$(SRC_DIR)
+COMPILE_ARGS    += -I$(SRC_DIR)
 
 else
 
 # Gate level simulation:
-SIM_BUILD				= sim_build/gl
+SIM_BUILD        = sim_build/gl
 COMPILE_ARGS    += -DGL_TEST
 COMPILE_ARGS    += -DFUNCTIONAL
 COMPILE_ARGS    += -DUSE_POWER_PINS

diff --git a/verilator/top.v b/verilator/top.v
@@ -8,6 +8,7 @@
 // `define VGA_12BPP
 // `define DVI
 
+`define NO_MACRO_ROMS
 `define QSPI_ROM
 
 module top  (