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Code cleanup after QSPI rom emu improvements.
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@rejunity
rejunity committed Nov 7, 2024
1 parent bc10cc0 commit f134630
Showing 1 changed file with 2 additions and 95 deletions.
97 changes: 2 additions & 95 deletions test/qspi_rom_emu.v
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Original file line number Diff line number Diff line change
Expand Up @@ -9,40 +9,6 @@ module qspi_rom_emu #(parameter ADDR_BITS = 24) (
output reg [3:0] data_out
);

// parameter DATA_WIDTH_BYTES = 1;
// localparam CMD = 8;
// localparam ADDR = CMD + ADDR_BITS/4; // receive address
// localparam LOAD = ADDR + 2; // load 2 bytes ahead: 1) 1st byte
// localparam INCA = LOAD + 1; // advance read addr
// localparam LOAD2 = LOAD + 2; // 2) 2nd byte
// localparam INC2 = LOAD + 3; // advance read addr
// localparam DATA = LOAD + 4; // serve data

// reg [7:0] counter;
// reg [ADDR_BITS-1:0] addr;
// always @(posedge clk) begin
// if (select) begin
// counter <= 0;
// end else begin
// counter <= counter + 1;
// if (counter < CMD) addr <= 0;
// else if (counter < ADDR) addr <= {addr[ADDR_BITS-1-4:0], cmd_addr_in};
// else if (counter < LOAD) data[15:8] <= rom[addr[11:0]];
// else if (counter < INCA) addr <= addr + 1;
// else if (counter < LOAD2) data[7:0] <= rom[addr[11:0]];
// else if (counter < INC2) addr <= addr + 1;
// else if (counter < DATA) data_out <= data[15-:4]; // 1st nibble
// else begin
// data_out <= data[11-:4]; // 2nd nibble
// // load next byte
// data[15:8] <= data[7:0];
// data[7:0] <= rom[addr[11:0]];
// addr <= addr + 1;
// counter <= counter - 1;
// end
// end
// end

parameter DATA_WIDTH_BYTES = 1;
localparam CMD = 8;
localparam ADDR = CMD + ADDR_BITS/4; // receive address
Expand All @@ -52,11 +18,12 @@ module qspi_rom_emu #(parameter ADDR_BITS = 24) (
localparam INC2 = LOAD + 3; // advance read addr
localparam DATA = LOAD + 4; // serve the data & load next byte

reg [ADDR_BITS-1:0] addr; // read address

reg sclk_prev; always @(posedge clk) sclk_prev <= sclk;
wire sclk_negedge = sclk_prev != sclk && !sclk;
reg [7:0] counter;

reg [ADDR_BITS-1:0] addr; // read address
always @(posedge clk) begin
if (select || reset) counter <= 0;
else if (sclk_negedge) begin
Expand All @@ -79,66 +46,6 @@ module qspi_rom_emu #(parameter ADDR_BITS = 24) (
end
end


// reg [7:0] counter; // counts on both positive and NEGATIVE clock edges
// wire [7:0] counter_negedge = counter[7:1];
// // always @(posedge clk or negedge clk) begin
// // if (select) counter <= 0;
// // else if (counter_negedge < DATA) counter <= counter + 1;
// // else counter <= counter - 3; // loop serving data
// // end

// reg reg_select;
// always @(posedge clk)
// if (reset)
// reg_select <= 1;
// else
// reg_select <= select;

// reg [ADDR_BITS-1:0] addr; // read address
// always @(posedge clk or negedge clk) begin // serves data on the NEGATIVE edge
// // if (select) counter <= 0;
// if (reg_select || reset) counter <= 0;
// else begin
// counter <= counter + 1;
// if (counter[0]) begin
// if (counter_negedge < CMD) addr <= 0;
// else if (counter_negedge < ADDR) addr <= {addr[ADDR_BITS-1-4:0], cmd_addr_in};
// else if (counter_negedge < LOAD) data[15:8] <= rom[addr[11:0]];
// else if (counter_negedge < INCA) addr <= addr + 1;
// else if (counter_negedge < LOAD2) data[7:0] <= rom[addr[11:0]];
// else if (counter_negedge < INC2) addr <= addr + 1;
// else if (counter_negedge < DATA) data_out <= data[15-:4]; // 1st nibble
// else begin
// data_out <= data[11-:4]; // 2nd nibble
// // load next byte
// data[15:8] <= data[7:0];
// data[7:0] <= rom[addr[11:0]];
// addr <= addr + 1;
// counter <= counter - 3;
// end
// end
// end
// end

// reg [ADDR_BITS-1:0] addr; // read address
// always @(negedge clk) begin // serves data on the NEGATIVE edge
// if (counter_negedge < CMD) addr <= 0;
// else if (counter_negedge < ADDR) addr <= {addr[ADDR_BITS-1-4:0], cmd_addr_in};
// else if (counter_negedge < LOAD) data[15:8] <= rom[addr[11:0]];
// else if (counter_negedge < INCA) addr <= addr + 1;
// else if (counter_negedge < LOAD2) data[7:0] <= rom[addr[11:0]];
// else if (counter_negedge < INC2) addr <= addr + 1;
// else if (counter_negedge < DATA) data_out <= data[15-:4]; // 1st nibble
// else begin
// data_out <= data[11-:4]; // 2nd nibble
// // load next byte
// data[15:8] <= data[7:0];
// data[7:0] <= rom[addr[11:0]];
// addr <= addr + 1;
// end
// end

reg [15:0] data;
reg [7:0] rom [4095:0];
initial begin
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