add riscv-semihosting
#170
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needed to cargo publish
fix typo in hprintln!
also fix `write_all` logic when the a single write doesn't write all the bytes
add a macro to write to the host stderr
Add `exit` and `report_exception` syscalls.
note that it's possible to skip the separate log file. closes #9
watch tail -> tail -f
drop write macros in favor of IO objects + fmt::Write
Stdio fixes after review See #11.
Merge upstream cortex-m-semihosting
Original documentation was largely an exact copy of cortex-m-semihosting at the fork. This commit fixes that, removing unnecessary references to cortex-m-semihosting and clearing out the changelog so that it's relevant to this repository instead.
The current repository CI was copied from cortex-m-semihosting, so it is not relevant to this one. In the future, it may be worthwhile to add some proper CI for this repo.
The old Cargo.toml was a bit out-of-date. This commit adds the RISC-V Team to the authors list, as well as bumping the version and edition to 1.59.0 and 2021.
This reverts commit f4c4830. It has been decided that the CI will be left in for now, and updated to work with this crate in the future.
Documentation and repository clean-up
The old CI was meant for cortex-m-semihosting, so it would not have worked with this repository, and it also used Travis CI, whereas the new one uses GitHub Actions. The CI runs `cargo check` for the following targets: - `riscv32i-unknown-none-elf` - `riscv32imc-unknown-none-elf` - `riscv32imac-unknown-none-elf` - `riscv64imac-unknown-none-elf` - `riscv64gc-unknown-none-elf` It also checks formatting and doc.
Currently, the library attempts to execute some semihosting operations in a completely interrupt-free context. It does this by using `riscv::interrupt::free`, which saves and restores the `mie` field of `mstatus`. As a result, attempts to initiate semihosting calls outside of M mode cause illegal instruction exceptions. This commit provides a solution, by requiring users to choose one of two features, "machine-mode" or "user-mode", which will compile different versions of the functions in src/export.rs that do and do not suspend interrupts, respectively. Failure to do so will throw a compiler error, unless the "no-semihosting" feature was enabled. A "supervisor-mode" feature was left out as the `riscv` crate does not yet have an equivalent of `interrupt::free` for supervisor mode. CI now also checks builds with both of these features.
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Is there a reason to not use the semihosting crate? It looks like it already supports RISCV, along with other arches. |
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To be honest, I didn't know this crate existed. It looks more complete than this PR, and it works perfectly in my rtic branch. The only reason I would accept this PR is to provide the exact same interface as What do you think about maintaining |
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What do you think about maintaining riscv-semihosting to mimic the cortex-m environment but leaving a section in the README.md file stating that the semihosting crate is way more complete and preferred for more professional development?
Sounds good! LGTM.
| asm!(" | ||
| .option push | ||
| .option norvc | ||
| slli x0, x0, 0x1f | ||
| ebreak | ||
| srai x0, x0, 0x7 | ||
| .option pop | ||
| ", | ||
| inout("a0") nr, | ||
| in("a1") _arg, |
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There appear to be two bugs in this asm call.
First, riscv-semihosting-spec says:
If paging is in use in the current mode, this sequence must not cross a page boundary as the semihosting system must be able to check for the semihosting sequence without needing data from potentially missing pages.
I believe you have to use .balign 16.
Second, some syscalls such as SYS_ELAPSED change a1, so I believe you have to use inout instead of in for a1.
(See also my semihosting crate for an example of RISC-V semihosting syscalls in Rust.)
I adapted
riscv-semihostingto the current fashion and added it to the workspace.The idea is that, by default, it assumes we run in machine mode (the same as in riscv and riscv-rt). The u-mode feature is used to cause exceptions if machine mode is not accesible.
I'm currently using it in my rtic branch for testing in QEMU and works as expected.