Add Mstatus helpers to allow setting fields in Mstatus

riscv/CHANGELOG.md

@@ -13,6 +13,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add `Mstatus::from(usize)` for use in unit tests
 - Add `Mstatus.bits()`
 - Add `Eq` and `PartialEq` for `pmpcfgx::{Range, Permission}`
+- Add `Mstatus::update_*` helpers to manipulate Mstatus values without touching
+  the CSR
 - Export `riscv::register::macros` module macros for external use
 
 ### Fixed

riscv/src/bits.rs

@@ -0,0 +1,17 @@
+/// Insert a new value into a bitfield
+///
+/// `value` is masked to `width` bits and inserted into `orig`.`
+#[inline]
+pub fn bf_insert(orig: usize, bit: usize, width: usize, value: usize) -> usize {
+    let mask = (1 << width) - 1;
+    orig & !(mask << bit) | ((value & mask) << bit)
+}
+
+/// Extract a value from a bitfield
+///
+/// Extracts `width` bits from bit offset `bit` and returns it shifted to bit 0.s
+#[inline]
+pub fn bf_extract(orig: usize, bit: usize, width: usize) -> usize {
+    let mask = (1 << width) - 1;
+    (orig >> bit) & mask
+}

riscv/src/lib.rs

@@ -36,6 +36,7 @@
 #![allow(clippy::missing_safety_doc)]
 
 pub mod asm;
+pub(crate) mod bits;
 pub mod delay;
 pub mod interrupt;
 pub mod register;

riscv/src/register/macros.rs

@@ -160,6 +160,34 @@ macro_rules! write_csr_rv32 {
     };
 }
 
+/// Convenience macro to write a value with `bits` to a CSR
+#[macro_export]
+macro_rules! write_csr_as {
+    ($csr_type:ty, $csr_number:literal) => {
+        $crate::write_csr!($csr_number);
+
+        /// Writes the CSR
+        #[inline]
+        pub fn write(value: $csr_type) {
+            unsafe { _write(value.bits) }
+        }
+    };
+}
+
+/// Convenience macro to write a value to a CSR register.
+#[macro_export]
+macro_rules! write_csr_as_rv32 {
+    ($csr_type:ty, $csr_number:literal) => {
+        $crate::write_csr_rv32!($csr_number);
+
+        /// Writes the CSR
+        #[inline]
+        pub fn write(value: $csr_type) {
+            unsafe { _write(value.bits) }
+        }
+    };
+}
+
 /// Convenience macro to write a [`usize`] value to a CSR register.
 #[macro_export]
 macro_rules! write_csr_as_usize {

riscv/src/register/misa.rs

@@ -11,9 +11,9 @@ pub struct Misa {
 /// Base integer ISA width
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
 pub enum XLEN {
-    XLEN32,
-    XLEN64,
-    XLEN128,
+    XLEN32 = 1,
+    XLEN64 = 2,
+    XLEN128 = 3,
 }
 
 impl XLEN {