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secworks/README.md

Welcome!

I'm Joachim Strömbergson, an embedded and hardware focused IT security consultant living in Gothenburg, Sweden. Out of passion as well as professionally, I develop open hardware implementations of cryptographic functions such as ciphers, hash functions, message authentication functions, random number generators. Several of my cores have been used in ASIC and FPGA designs. Please check the status information in the README of the core you are interested in for its readiness and maturity.

For custom core development, adaptions to your specific needs and integration assistance, please contact me.

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  1. aes aes Public

    Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

    Verilog 340 126

  2. chacha chacha Public

    Verilog 2001 implementation of the ChaCha stream cipher.

    Verilog 38 14

  3. sha256 sha256 Public

    Hardware implementation of the SHA-256 cryptographic hash function

    Verilog 321 89

  4. blake2s blake2s Public

    Verilog implementation of the 32-bit version of the Blake2 hash function

    Verilog 21 8

  5. prince prince Public

    The Prince lightweight block cipher in Verilog.

    Verilog 7 5

  6. poly1305 poly1305 Public

    Hardware implementation of the poly1305 message authentication function.

    Verilog 8 3