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1. RPHAX RPHAX Public

   RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Tem…

   Tcl 16

2. Physical-Design-with-OpenLANE-using-SKY130-PDK Physical-Design-with-OpenLANE-using-SKY130-PDK Public

   This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSI…

   Verilog 37 7

3. TL-X-org/tlvflows TL-X-org/tlvflows Public

   Tcl

4. Accelerating_Standard_and_Modified_AES128 Accelerating_Standard_and_Modified_AES128 Public

   Forked from BalaDhinesh/Accelerating_Standard_and_Modified_AES128

   Verilog

5. 1st-CLaaS 1st-CLaaS Public

   Forked from os-fpga/1st-CLaaS

   Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

   C

6. warp-v warp-v Public

   Forked from stevehoover/warp-v

   WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

   JavaScript