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Merge pull request #55 from slaclab/pre-release
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Release Candidate v5.10.0
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@ruck314
ruck314 authored Feb 6, 2024
2 parents 688387b + ee6e572 commit 876dc60
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Showing 8 changed files with 62 additions and 4 deletions.
2 changes: 1 addition & 1 deletion conda-recipe/meta.yaml
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@@ -1,4 +1,4 @@
package:
package:
name: lcls2_pgp_fw_lib
version: {{ GIT_DESCRIBE_TAG }}

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4 changes: 3 additions & 1 deletion hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Hsio.vhd
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Expand Up @@ -243,6 +243,7 @@ begin
-- Trigger Interface
trigger => remoteTriggers(i),
triggerCode => triggerCodes(i),
triggerPause => eventTrigMsgCtrl(0).pause,
-- QPLL Interface
qpllLock => qpllLock(i),
qpllClk => qpllClk(i),
Expand Down Expand Up @@ -280,6 +281,7 @@ begin
-- Trigger Interface
trigger => remoteTriggers(i),
triggerCode => triggerCodes(i),
triggerPause => eventTrigMsgCtrl(0).pause,
-- PGP Serial Ports
pgpRxP => qsfp0RxP(i),
pgpRxN => qsfp0RxN(i),
Expand Down Expand Up @@ -323,7 +325,7 @@ begin
U_TimingRx : entity lcls2_pgp_fw_lib.TimingRx
generic map (
TPD_G => TPD_G,
USE_GT_REFCLK_G => true, -- TRUE: refClkP/N
USE_GT_REFCLK_G => true, -- TRUE: refClkP/N
SIMULATION_G => ROGUE_SIM_EN_G,
DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G,
AXIL_CLK_FREQ_G => AXIL_CLK_FREQ_G,
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2 changes: 2 additions & 0 deletions hardware/XilinxKcu1500/rtl/Kcu1500Hsio.vhd
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Expand Up @@ -265,6 +265,7 @@ begin
-- Trigger Interface
trigger => remoteTriggers(i),
triggerCode => triggerCodes(i),
triggerPause => eventTrigMsgCtrl(0).pause,
-- QPLL Interface
qpllLock => qpllLock(i),
qpllClk => qpllClk(i),
Expand Down Expand Up @@ -302,6 +303,7 @@ begin
-- Trigger Interface
trigger => remoteTriggers(i),
triggerCode => triggerCodes(i),
triggerPause => eventTrigMsgCtrl(0).pause,
-- PGP Serial Ports
pgpRxP => qsfp0RxP(i),
pgpRxN => qsfp0RxN(i),
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2 changes: 2 additions & 0 deletions hardware/XilinxVariumC1100/rtl/C1100Hsio.vhd
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Expand Up @@ -254,6 +254,7 @@ begin
-- Trigger Interface
trigger => remoteTriggers(i),
triggerCode => triggerCodes(i),
triggerPause => eventTrigMsgCtrl(0).pause,
-- QPLL Interface
qpllLock => qpllLock(i),
qpllClk => qpllClk(i),
Expand Down Expand Up @@ -291,6 +292,7 @@ begin
-- Trigger Interface
trigger => remoteTriggers(i),
triggerCode => triggerCodes(i),
triggerPause => eventTrigMsgCtrl(0).pause,
-- PGP Serial Ports
pgpRxP => qsfp0RxP(i),
pgpRxN => qsfp0RxN(i),
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13 changes: 13 additions & 0 deletions shared/rtl/UltraScale+/Pgp2bLane.vhd
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Expand Up @@ -39,6 +39,7 @@ entity Pgp2bLane is
-- Trigger Interface
trigger : in sl;
triggerCode : in slv(7 downto 0) := (others => '0');
triggerPause : in sl;
-- PGP Serial Ports
pgpTxP : out sl;
pgpTxN : out sl;
Expand Down Expand Up @@ -95,8 +96,20 @@ architecture mapping of Pgp2bLane is
signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0);
signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0);

signal triggerPauseVec : slv(7 downto 0);

begin

triggerPauseVec <= (others => triggerPause);
U_triggerPause : entity surf.SynchronizerVector
generic map (
TPD_G => TPD_G,
WIDTH_G => 8)
port map (
clk => pgpTxClk,
dataIn => triggerPauseVec,
dataOut => locTxIn.locData);

U_Trig : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G)
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15 changes: 14 additions & 1 deletion shared/rtl/UltraScale+/Pgp4Lane.vhd
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Expand Up @@ -36,7 +36,8 @@ entity Pgp4Lane is
port (
-- Trigger Interface
trigger : in sl;
triggerCode : in slv(7 downto 0);
triggerCode : in slv(7 downto 0) := (others => '0');
triggerPause : in sl;
-- QPLL Interface
qpllLock : in slv(1 downto 0);
qpllClk : in slv(1 downto 0);
Expand Down Expand Up @@ -95,8 +96,20 @@ architecture mapping of Pgp4Lane is
signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0);
signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0);

signal triggerPauseVec : slv(47 downto 0);

begin

triggerPauseVec <= (others => triggerPause);
U_triggerPause : entity surf.SynchronizerVector
generic map (
TPD_G => TPD_G,
WIDTH_G => 48)
port map (
clk => pgpClk,
dataIn => triggerPauseVec,
dataOut => pgpTxIn.locData);

U_Trig : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G)
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13 changes: 13 additions & 0 deletions shared/rtl/UltraScale/Pgp2bLane.vhd
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Expand Up @@ -39,6 +39,7 @@ entity Pgp2bLane is
-- Trigger Interface
trigger : in sl;
triggerCode : in slv(7 downto 0) := (others => '0');
triggerPause : in sl;
-- PGP Serial Ports
pgpTxP : out sl;
pgpTxN : out sl;
Expand Down Expand Up @@ -95,8 +96,20 @@ architecture mapping of Pgp2bLane is
signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0);
signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0);

signal triggerPauseVec : slv(7 downto 0);

begin

triggerPauseVec <= (others => triggerPause);
U_triggerPause : entity surf.SynchronizerVector
generic map (
TPD_G => TPD_G,
WIDTH_G => 8)
port map (
clk => pgpTxClk,
dataIn => triggerPauseVec,
dataOut => locTxIn.locData);

U_Trig : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G)
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15 changes: 14 additions & 1 deletion shared/rtl/UltraScale/Pgp4Lane.vhd
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Expand Up @@ -37,7 +37,8 @@ entity Pgp4Lane is
port (
-- Trigger Interface
trigger : in sl;
triggerCode : in slv(7 downto 0);
triggerCode : in slv(7 downto 0) := (others => '0');
triggerPause : in sl;
-- QPLL Interface
qpllLock : in slv(1 downto 0);
qpllClk : in slv(1 downto 0);
Expand Down Expand Up @@ -96,8 +97,20 @@ architecture mapping of Pgp4Lane is
signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0);
signal pgpRxSlaves : AxiStreamSlaveArray(3 downto 0);

signal triggerPauseVec : slv(47 downto 0);

begin

triggerPauseVec <= (others => triggerPause);
U_triggerPause : entity surf.SynchronizerVector
generic map (
TPD_G => TPD_G,
WIDTH_G => 48)
port map (
clk => pgpClk,
dataIn => triggerPauseVec,
dataOut => pgpTxIn.locData);

U_Trig : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G)
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