Increasing NUM_DETECTORS_G range from 4 to 8

slaclab · Mar 1, 2024 · cd77b31 · cd77b31
1 parent 9ec47f7
commit cd77b31
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/shared/rtl/UltraScale/TimingRx.vhd b/shared/rtl/UltraScale/TimingRx.vhd
@@ -42,7 +42,7 @@ entity TimingRx is
       AXIL_CLK_FREQ_G     : real    := 156.25E+6;  -- units of Hz
       DMA_AXIS_CONFIG_G   : AxiStreamConfigType;
       AXI_BASE_ADDR_G     : slv(31 downto 0);
-      NUM_DETECTORS_G     : integer range 1 to 4;
+      NUM_DETECTORS_G     : integer range 1 to 8;
       EN_LCLS_I_TIMING_G  : boolean := false;
       EN_LCLS_II_TIMING_G : boolean := true);
    port (