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Merge pull request #2463 from fpistm/STM32CubeH5_update
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chore(h5): update to latest STM32CubeH5 v1.3.0
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@fpistm
fpistm authored Jul 24, 2024
2 parents 98d0569 + b7c5efc commit 4f59a20
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Showing 104 changed files with 2,799 additions and 1,264 deletions.
2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h
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Expand Up @@ -505,7 +505,7 @@
#define NVIC_INIT_ITNS3 1

/*
// Interrupts 96..127
// Interrupts 96..124
// <o.0> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
// <o.1> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
// <o.7> FPU_IRQn <0=> Secure state <1=> Non-Secure state
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2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h
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Expand Up @@ -506,7 +506,7 @@
#define NVIC_INIT_ITNS3 1

/*
// Interrupts 96..127
// Interrupts 96..124
// <o.0> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
// <o.1> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
// <o.7> FPU_IRQn <0=> Secure state <1=> Non-Secure state
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78 changes: 35 additions & 43 deletions system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
Expand Down Expand Up @@ -175,7 +175,7 @@ typedef enum

/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __SAUREGION_PRESENT 0U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */
Expand Down Expand Up @@ -349,7 +349,6 @@ typedef struct
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
uint32_t RESERVED;
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
} RNG_TypeDef;

Expand Down Expand Up @@ -1064,10 +1063,8 @@ typedef struct

typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x300 + 0x00 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;


Expand Down Expand Up @@ -1262,12 +1259,10 @@ typedef struct
#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL)
#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL)
#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL)

#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)


/*!< APB3 Non secure peripherals */
#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL)
#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL)
Expand All @@ -1284,12 +1279,10 @@ typedef struct

/* Debug MCU registers base address */
#define DBGMCU_BASE (0x44024000UL)

#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */
#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */


/* Internal Flash OTP Area */
#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */
Expand Down Expand Up @@ -3044,11 +3037,16 @@ typedef struct
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk


/******************** Bits definition for RNG_HTCR register *******************/
#define RNG_HTCR_HTCFG_Pos (0U)
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk

/******************** RNG Nist Compliance Values ******************************/
#define RNG_CR_NIST_VALUE (0x00F00D00U)
#define RNG_HTCR_NIST_VALUE (0xAAC7U)

/******************************************************************************/
/* */
/* Digital to Analog Converter */
Expand Down Expand Up @@ -4368,26 +4366,26 @@ typedef struct
#define EXTI_PRIVENR1_PRIV29 EXTI_PRIVENR1_PRIV29_Msk /*!< Privilege enable on line 29 */

/****************** Bit definition for EXTI_RTSR2 register *******************/
#define EXTI_RTSR2_TR_Pos (16U)
#define EXTI_RTSR2_TR_Msk (0x24UL << EXTI_RTSR2_TR_Pos) /*!< 0x00240000 */
#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
#define EXTI_RTSR2_TR50_Pos (18U)
#define EXTI_RTSR2_TR50_Msk (0x1UL << EXTI_RTSR2_TR50_Pos) /*!< 0x00040000 */
#define EXTI_RTSR2_TR50 EXTI_RTSR2_TR50_Msk /*!< Rising trigger event configuration bit of line 50 */
#define EXTI_RTSR2_TR53_Pos (21U)
#define EXTI_RTSR2_TR53_Msk (0x1UL << EXTI_RTSR2_TR53_Pos) /*!< 0x00200000 */
#define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */
#define EXTI_RTSR2_RT_Pos (16U)
#define EXTI_RTSR2_RT_Msk (0x24UL << EXTI_RTSR2_RT_Pos) /*!< 0x00240000 */
#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */
#define EXTI_RTSR2_RT50_Pos (18U)
#define EXTI_RTSR2_RT50_Msk (0x1UL << EXTI_RTSR2_RT50_Pos) /*!< 0x00040000 */
#define EXTI_RTSR2_RT50 EXTI_RTSR2_RT50_Msk /*!< Rising trigger event configuration bit of line 50 */
#define EXTI_RTSR2_RT53_Pos (21U)
#define EXTI_RTSR2_RT53_Msk (0x1UL << EXTI_RTSR2_RT53_Pos) /*!< 0x00200000 */
#define EXTI_RTSR2_RT53 EXTI_RTSR2_RT53_Msk /*!< Rising trigger event configuration bit of line 53 */

/****************** Bit definition for EXTI_FTSR2 register *******************/
#define EXTI_FTSR2_TR_Pos (16U)
#define EXTI_FTSR2_TR_Msk (0x24 << EXTI_FTSR2_TR_Pos) /*!< 0x00240000 */
#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
#define EXTI_FTSR2_TR50_Pos (18U)
#define EXTI_FTSR2_TR50_Msk (0x1UL << EXTI_FTSR2_TR50_Pos) /*!< 0x00040000 */
#define EXTI_FTSR2_TR50 EXTI_FTSR2_TR50_Msk /*!< Falling trigger event configuration bit of line 50 */
#define EXTI_FTSR2_TR53_Pos (21U)
#define EXTI_FTSR2_TR53_Msk (0x1UL << EXTI_FTSR2_TR53_Pos) /*!< 0x00200000 */
#define EXTI_FTSR2_TR53 EXTI_FTSR2_TR53_Msk /*!< Falling trigger event configuration bit of line 53 */
#define EXTI_FTSR2_FT_Pos (16U)
#define EXTI_FTSR2_FT_Msk (0x24 << EXTI_FTSR2_FT_Pos) /*!< 0x00240000 */
#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */
#define EXTI_FTSR2_FT50_Pos (18U)
#define EXTI_FTSR2_FT50_Msk (0x1UL << EXTI_FTSR2_FT50_Pos) /*!< 0x00040000 */
#define EXTI_FTSR2_FT50 EXTI_FTSR2_FT50_Msk /*!< Falling trigger event configuration bit of line 50 */
#define EXTI_FTSR2_FT53_Pos (21U)
#define EXTI_FTSR2_FT53_Msk (0x1UL << EXTI_FTSR2_FT53_Pos) /*!< 0x00200000 */
#define EXTI_FTSR2_FT53 EXTI_FTSR2_FT53_Msk /*!< Falling trigger event configuration bit of line 53 */

/****************** Bit definition for EXTI_SWIER2 register ******************/
#define EXTI_SWIER2_SWIER50_Pos (18U)
Expand Down Expand Up @@ -5580,10 +5578,10 @@ typedef struct

/****************** Bits definition for FLASH_HDPEXTR register *****************/
#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U)
#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */
#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7UL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x00000007 */
#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */
#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U)
#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */
#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7UL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x00070000 */
#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */

/******************* Bits definition for FLASH_OPTSR register ***************/
Expand Down Expand Up @@ -7273,27 +7271,27 @@ typedef struct

/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */

/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */

/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */

/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand All @@ -7307,7 +7305,7 @@ typedef struct

/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */

/******************* Bit definition for TIM_BDTR register *******************/
Expand Down Expand Up @@ -9099,9 +9097,6 @@ typedef struct
#define RCC_AHB2LPENR_RNGLPEN_Pos (18U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
#define RCC_AHB2LPENR_PKALPEN_Pos (19U)
#define RCC_AHB2LPENR_PKALPEN_Msk (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos) /*!< 0x00080000 */
#define RCC_AHB2LPENR_PKALPEN RCC_AHB2LPENR_PKALPEN_Msk
#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
Expand Down Expand Up @@ -10901,8 +10896,6 @@ typedef struct
#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos)
#define GTZC_CFGR3_RNG_Pos (18U)
#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos)
#define GTZC_CFGR3_PKA_Pos (20U)
#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos)
#define GTZC_CFGR3_RAMCFG_Pos (26U)
#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos)

Expand Down Expand Up @@ -11004,8 +10997,6 @@ typedef struct
#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk
#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos
#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk
#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos
#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk
#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos
#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk

Expand All @@ -11018,6 +11009,7 @@ typedef struct
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
#define USART_DMAREQUESTS_SW_WA
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
Expand Down
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