Verilog modules for beginners
-
Updated
May 27, 2022 - Verilog
Verilog modules for beginners
This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
5-stage pipelined 32-bit MIPS microprocessor in Verilog
Курс по программированию ПЛИС с примерами
Some examples of Veitch-Karnaugh maps solved using verilog language developed as coursework of Architecture and Computer Organization I- @puc Minas
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani
A coocbook of HDL (primarily Verilog) modules
Add a description, image, and links to the verilog-snippets topic page so that developers can more easily learn about it.
To associate your repository with the verilog-snippets topic, visit your repo's landing page and select "manage topics."