dont use fpu as default

config for auto ci
whutddk · Feb 5, 2024 · d669af0 · d669af0
1 parent 9130e60
commit d669af0
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Showing 7 changed files with 108 additions and 68 deletions.
diff --git a/.github/workflows/BuildAndTest.yml b/.github/workflows/BuildAndTest.yml
@@ -4,7 +4,7 @@ name: ChiselStage
 on:
   # Triggers the workflow on push or pull request events but only for the master branch
   push:
-    branches: [ master, develop ]
+    branches: [ master, develop, bump/mill_chisel5 ]
   # pull_request:
   #   branches: [ master ]
 
@@ -19,14 +19,14 @@ jobs:
     runs-on: [self-hosted, Linux, X64]
     name: chiselStage
     container:
-      image: whutddk/rift2env:riscvtest
+      image: whutddk/rift2env:chisel5
     # needs: clean
     # Steps represent a sequence of tasks that will be executed as part of the job
     steps:
       - name: set up apt
         run: |
           apt-get update
-          apt-get install -y wget git make
+          apt-get install -y wget git make curl
 
 
       - uses: actions/checkout@v3.3.0
@@ -41,8 +41,10 @@ jobs:
       - name: Compile
         run: |
           echo ${GITHUB_WORKSPACE}
-          sbt "test:runMain test.testAll"
-          sbt doc
+
+          mill -i rift2Core[chisel].test.runMain test.testAll
+          mill --no-server show rift2Core[chisel].docJar
+          unzip -d ScalaDoc/ out/rift2Core/chisel/docJar.dest/out.jar
 
           echo $GITHUB_REF_NAME
           
@@ -53,19 +55,19 @@ jobs:
 
           cp ${GITHUB_WORKSPACE}/LICENSE.Apache ${GITHUB_WORKSPACE}/../
           cp ${GITHUB_WORKSPACE}/LICENSE.NPL ${GITHUB_WORKSPACE}/../
-          cp -R target/scala-2.13/api ${GITHUB_WORKSPACE}/../ScalaDoc/$GITHUB_REF_NAME
-
-          cd ${GITHUB_WORKSPACE}/generated/Release/
-          tar -cvf Rift2300-Release.tar Rift2300/*
-          tar -cvf Rift2310-Release.tar Rift2310/*
-          tar -cvf Rift2320-Release.tar Rift2320/*
-          tar -cvf Rift2330-Release.tar Rift2330/*
-          tar -cvf Rift2340-Release.tar Rift2340/*
-          tar -cvf Rift2350-Release.tar Rift2350/*
-          tar -cvf Rift2360-Release.tar Rift2360/*
-          tar -cvf Rift2370-Release.tar Rift2370/*
-          tar -cvf Rift2380-Release.tar Rift2380/*
-          tar -cvf Rift2390-Release.tar Rift2390/*
+          cp -R ScalaDoc/* ${GITHUB_WORKSPACE}/../ScalaDoc/$GITHUB_REF_NAME
+
+          # cd ${GITHUB_WORKSPACE}/generated/Release/
+          # tar -cvf Rift2300-Release.tar Rift2300/*
+          # tar -cvf Rift2310-Release.tar Rift2310/*
+          # tar -cvf Rift2320-Release.tar Rift2320/*
+          # tar -cvf Rift2330-Release.tar Rift2330/*
+          # tar -cvf Rift2340-Release.tar Rift2340/*
+          # tar -cvf Rift2350-Release.tar Rift2350/*
+          # tar -cvf Rift2360-Release.tar Rift2360/*
+          # tar -cvf Rift2370-Release.tar Rift2370/*
+          # tar -cvf Rift2380-Release.tar Rift2380/*
+          # tar -cvf Rift2390-Release.tar Rift2390/*
 
           cd ${GITHUB_WORKSPACE}/generated/Debug/
           tar -cvf Rift2300-Debug.tar  Rift2300/*
@@ -124,25 +126,25 @@ jobs:
           prerelease: true
           target_commitish: ${{github.ref_name}}
           files: |
-            ./generated/Release/Rift2300-Release.tar
+            # ./generated/Release/Rift2300-Release.tar
             ./generated/Debug/Rift2300-Debug.tar
-            ./generated/Release/Rift2310-Release.tar
+            # ./generated/Release/Rift2310-Release.tar
             ./generated/Debug/Rift2310-Debug.tar
-            ./generated/Release/Rift2320-Release.tar
+            # ./generated/Release/Rift2320-Release.tar
             ./generated/Debug/Rift2320-Debug.tar
-            ./generated/Release/Rift2330-Release.tar
+            # ./generated/Release/Rift2330-Release.tar
             ./generated/Debug/Rift2330-Debug.tar
-            ./generated/Release/Rift2340-Release.tar
+            # ./generated/Release/Rift2340-Release.tar
             ./generated/Debug/Rift2340-Debug.tar
-            ./generated/Release/Rift2350-Release.tar
+            # ./generated/Release/Rift2350-Release.tar
             ./generated/Debug/Rift2350-Debug.tar
-            ./generated/Release/Rift2360-Release.tar
+            # ./generated/Release/Rift2360-Release.tar
             ./generated/Debug/Rift2360-Debug.tar
-            ./generated/Release/Rift2370-Release.tar
+            # ./generated/Release/Rift2370-Release.tar
             ./generated/Debug/Rift2370-Debug.tar
-            ./generated/Release/Rift2380-Release.tar
+            # ./generated/Release/Rift2380-Release.tar
             ./generated/Debug/Rift2380-Debug.tar
-            ./generated/Release/Rift2390-Release.tar
+            # ./generated/Release/Rift2390-Release.tar
             ./generated/Debug/Rift2390-Debug.tar
             ./LICENSE.Apache
             ./LICENSE.NPL
@@ -160,25 +162,25 @@ jobs:
           prerelease: false
           target_commitish: ${{github.ref_name}}
           files: |
-            ./generated/Release/Rift2300-Release.tar
+            # ./generated/Release/Rift2300-Release.tar
             ./generated/Debug/Rift2300-Debug.tar
-            ./generated/Release/Rift2310-Release.tar
+            # ./generated/Release/Rift2310-Release.tar
             ./generated/Debug/Rift2310-Debug.tar
-            ./generated/Release/Rift2320-Release.tar
+            # ./generated/Release/Rift2320-Release.tar
             ./generated/Debug/Rift2320-Debug.tar
-            ./generated/Release/Rift2330-Release.tar
+            # ./generated/Release/Rift2330-Release.tar
             ./generated/Debug/Rift2330-Debug.tar
-            ./generated/Release/Rift2340-Release.tar
+            # ./generated/Release/Rift2340-Release.tar
             ./generated/Debug/Rift2340-Debug.tar
-            ./generated/Release/Rift2350-Release.tar
+            # ./generated/Release/Rift2350-Release.tar
             ./generated/Debug/Rift2350-Debug.tar
-            ./generated/Release/Rift2360-Release.tar
+            # ./generated/Release/Rift2360-Release.tar
             ./generated/Debug/Rift2360-Debug.tar
-            ./generated/Release/Rift2370-Release.tar
+            # ./generated/Release/Rift2370-Release.tar
             ./generated/Debug/Rift2370-Debug.tar
-            ./generated/Release/Rift2380-Release.tar
+            # ./generated/Release/Rift2380-Release.tar
             ./generated/Debug/Rift2380-Debug.tar
-            ./generated/Release/Rift2390-Release.tar
+            # ./generated/Release/Rift2390-Release.tar
             ./generated/Debug/Rift2390-Debug.tar
             ./LICENSE.Apache
             ./LICENSE.NPL
@@ -253,7 +255,7 @@ jobs:
           cd /Rift2Core
 
           wget https://github.com/whutddk/Rift2Core/releases/download/${{ steps.getrelease.outputs.tag_name }}/${{matrix.version}}-Debug.tar
-          wget https://github.com/whutddk/Rift2Core/releases/download/${{ steps.getrelease.outputs.tag_name }}/${{matrix.version}}-Release.tar
+          # wget https://github.com/whutddk/Rift2Core/releases/download/${{ steps.getrelease.outputs.tag_name }}/${{matrix.version}}-Release.tar
 
 
 
@@ -262,10 +264,10 @@ jobs:
           cd /Rift2Core
           
           mkdir -p ./generated/Debug
-          mkdir -p ./generated/Release
+          # mkdir -p ./generated/Release
           
           tar -xvf ./${{matrix.version}}-Debug.tar -C ./generated/Debug
-          tar -xvf ./${{matrix.version}}-Release.tar -C ./generated/Release
+          # tar -xvf ./${{matrix.version}}-Release.tar -C ./generated/Release
 
 
 

diff --git a/.gitignore b/.gitignore
@@ -367,3 +367,4 @@ VSimTop
 tb/sw/opensbi/fw_jump.dep
 tb/sw/opensbi/fw_jump.elf.ld
 mill
+ScalaDoc/
diff --git a/Makefile b/Makefile
@@ -260,7 +260,7 @@ isa ?= $(aluisa) $(bruisa) $(lsuisa) $(privisa) $(mulisa)# $(fpuisa)
 
 
 
-.PHONY: compile clean VSimTop mill
+.PHONY: compile clean VSimTop mill doc
 
 module:
 	sbt "test:runMain test.testModule --target-dir generated --show-registrations --full-stacktrace -E verilog"
@@ -278,8 +278,13 @@ compile:
 
 mill:
 	rm -rf ./generated/Main/
+	./mill --no-server clean
 	./mill -i rift2Core[chisel].test.runMain test.testMain
 
+doc:
+	./mill --no-server show rift2Core[chisel].docJar
+	unzip -d ScalaDoc/ out/rift2Core/chisel/docJar.dest/out.jar
+
 noc:
 	rm -rf ./generated/Main/
 	sbt "test:runMain test.testNoC \
@@ -288,8 +293,9 @@ noc:
 
 line: 
 	rm -rf generated/Debug/
-	rm -rf generated/Release/
-	sbt "test:runMain test.testAll"
+	# rm -rf generated/Release/
+	./mill --no-server clean
+	./mill -i rift2Core[chisel].test.runMain test.testAll
 
 CONFIG ?= /Main/
 

diff --git a/src/docker/chisel5.do b/src/docker/chisel5.do
@@ -0,0 +1,15 @@
+FROM whutddk/rift2env:riscvtest
+
+ENV RISCV=/RISCV/ PATH=$PATH:/RISCV/bin:/RISCV/lib:$YOSYS/bin:/firtool-1.59.0/bin
+
+RUN    apt-get update \
+	&& apt-get install -y curl wget zip\
+	&& cd /usr/local/bin \
+    && curl -L https://raw.githubusercontent.com/lefou/millw/0.4.11/millw > mill && chmod +x mill \
+    && cd / \
+    && wget https://github.com/llvm/circt/releases/download/firtool-1.59.0/circt-full-shared-linux-x64.tar.gz \
+    && tar -zxvf circt-full-shared-linux-x64.tar.gz \
+    && rm circt-full-shared-linux-x64.tar.gz \
+    && apt-get purge -y --auto-remove curl wget \
+    && apt-get clean \
+    && rm -rf /var/lib/apt/lists/*
diff --git a/src/main/scala/Config.scala b/src/main/scala/Config.scala
@@ -62,7 +62,6 @@ class Rift2300 extends Config((_, _, _) => {
     ),
 
     dptEntry = 1,
-    fpuNum = 0,
     mulNum = 0,
 
     isMinArea = true,
@@ -126,7 +125,6 @@ class Rift2310 extends Config((_, _, _) => {
     ),
 
     dptEntry = 2,
-    fpuNum = 0,
     mulNum = 1,
 
     isMinArea = true,
@@ -186,7 +184,6 @@ class Rift2320 extends Config((_, _, _) => {
     ),
 
     dptEntry = 4,
-    fpuNum = 0,
     mulNum = 1,
 
     isMinArea = true,
@@ -244,7 +241,6 @@ class Rift2330 extends Config((_, _, _) => {
     ),
 
     dptEntry = 4,
-    fpuNum = 0,
 
     isMinArea = true,
     isLowPower = false,
@@ -300,7 +296,6 @@ class Rift2330D extends Config((_, _, _) => {
     ),
 
     dptEntry = 1,
-    fpuNum = 0,
     mulNum = 0,
 
     isMinArea = true,
@@ -345,7 +340,6 @@ class Rift2340 extends Config((_, _, _) => {
     ),
 
     dptEntry = 6,
-    fpuNum = 1,
 
     isMinArea = true,
     isLowPower = false,
@@ -388,7 +382,6 @@ class Rift2350 extends Config((_, _, _) => {
     ),
 
     dptEntry = 8,
-    fpuNum = 0,
 
     isMinArea = true,
     isLowPower = false,
@@ -431,7 +424,6 @@ class Rift2360 extends Config((_, _, _) => {
     ),
 
     dptEntry = 12,
-    fpuNum = 0,
 
     isMinArea = false,
     isLowPower = true,
@@ -517,7 +509,6 @@ class Rift2380 extends Config((_, _, _) => {
     ),
 
     dptEntry = 24,
-    fpuNum = 1,
     isMinArea = false,
     isLowPower = true,
   )
@@ -559,7 +550,6 @@ class Rift2390 extends Config((_, _, _) => {
     ),
 
     dptEntry = 32,
-    fpuNum = 1,
 
     isMinArea = false,
     isLowPower = true,

diff --git a/src/main/scala/Parameters.scala b/src/main/scala/Parameters.scala
@@ -207,7 +207,7 @@ case class RiftSetting(
 
   aluNum: Int = 2,
   mulNum: Int = 1,
-  fpuNum: Int = 1,
+  fpuNum: Int = 0,
 
   vectorParameters: VectorParameters = VectorParameters(),
 

diff --git a/src/test/scala/rift2Core/rift2Chip_tb.scala b/src/test/scala/rift2Core/rift2Chip_tb.scala
@@ -39,7 +39,7 @@ object testMain extends App {
   // val cfg = new NormalCfg
   // val cfg = new Rift2GoCfg
   // val cfg = new Rift2350
-  val cfg = new Rift2370
+  val cfg = new Rift2330
 
 
   // circt.stage.ChiselStage.emitSystemVerilogFile(
@@ -63,7 +63,22 @@ object testMain extends App {
       circt.stage.FirtoolOption("--disable-annotation-unknown"),
       circt.stage.FirtoolOption( "--dedup"),
     )
+
   )
+
+  // val fir = circt.stage.ChiselStage.emitCHIRRTL(
+  //   gen =  LazyModule(new Rift2Chip()(cfg)).module,
+  //   args = Array(
+  //     // "--target-dir", "generated/Main",
+  //     // "--target", "verilog",
+  //     // "--split-verilog",
+  //     // "--split-verilog",
+  //     ) ++ args,
+  // )
+  // import java.io._
+  // val writer = new PrintWriter(new File("Rift2Chip.fir" ))
+  // writer.write(s"$fir")
+  // writer.close()
 }
 
 // object testNoC extends App {
@@ -129,19 +144,30 @@ object testAll extends App {
   config.map{ cfg =>
     println("Compiling " + cfg._2)
 
-    (new circt.stage.ChiselStage).execute( Array( "--target-dir", "generated/Release/"++cfg._2, "-E", "verilog" ) ++ args, Seq(
-        ChiselGeneratorAnnotation(() => {
-      val soc = LazyModule(new Rift2Chip(isFlatten = true)(cfg._1))
-      soc.module
-    })
-    ))
+    // (new circt.stage.ChiselStage).execute( Array( "--target-dir", "generated/Release/"++cfg._2, "-E", "verilog" ) ++ args, Seq(
+    //     ChiselGeneratorAnnotation(() => {
+    //   val soc = LazyModule(new Rift2Chip(isFlatten = true)(cfg._1))
+    //   soc.module
+    // })
+    // ))
+
+    (new circt.stage.ChiselStage).execute(
+      Array(
+        "--target-dir", "generated/Debug/"++cfg._2,
+        "--target", "verilog",
+        "--split-verilog",
+        ) ++ args,
+      Seq(
+        chisel3.stage.ChiselGeneratorAnnotation( () => {
+          val soc = LazyModule(new Rift2Chip(isFlatten = false)(cfg._1))
+          soc.module
+        }),
+        circt.stage.FirtoolOption("--disable-annotation-unknown"),
+        circt.stage.FirtoolOption( "--dedup"),
+      )
+    )
+
 
-    (new circt.stage.ChiselStage).execute( Array( "--target-dir", "generated/Debug/"++cfg._2, "-e", "verilog" ) ++ args, Seq(
-        ChiselGeneratorAnnotation(() => {
-      val soc = LazyModule(new Rift2Chip(isFlatten = false)(cfg._1))
-      soc.module
-    })
-    ))
   }
 }