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Support for building wolfBoot for the network core (make CORE=2).
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@dgarske
dgarske committed Sep 10, 2024
1 parent 9e6c1be commit e54b419
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15 changes: 13 additions & 2 deletions docs/Targets.md
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Expand Up @@ -2127,11 +2127,18 @@ Example of flash memory layout and configuration on the nRF52:
## Nordic nRF5340
Tested with the Nordic nRF5340-DK.
Tested with the Nordic nRF5340-DK. This device has two cores:
1) Application core: Cortex-M33 at 128MHz, w/TrustZone, 1MB flash, 512KB RAM
2) Network core: Cortex-M33 at 64MHz, 256KB Flash and 64KB RAM
The cores communicate using the IPC peripheral.
### Building Nordic nRF5340
Setup the configuration to build: `cp config/examples/nrf5340.config .config`
Build using `make clean && make`
Build application core loading using: `make clean && make`
Build network core loader using: `make CORE=2`
Flashing with JLink:
Expand All @@ -2142,6 +2149,10 @@ loadbin factory.bin 0x0
rnh
```

Note: For network core use: `-device nRF5340_xxAA_NET`

### Debugging Nordic nRF5340

Debugging with JLink:

1) Start GDB Server:
Expand Down
273 changes: 162 additions & 111 deletions hal/nrf5340.h
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Expand Up @@ -22,11 +22,25 @@
#ifndef _HAL_NRF5340_H_
#define _HAL_NRF5340_H_

#ifndef TZEN
#define TZEN
/* Build-time gate for secure or non-secure peripherals.
* At boot-time peripherals are secure */
#if defined(CORE) && CORE == 2
#define TARGET_nrf5340_NET /* core 2 */

#undef QSPI_FLASH /* not supported on network core */
#else
#define TARGET_nrf5340_APP /* core 1 */
#ifndef TZEN
#define TZEN
#endif
#endif

#ifdef TARGET_nrf5340_APP
#define CPU_CLOCK 128000000UL /* 128MHz */
#else
#define CPU_CLOCK 64000000UL /* 64MHz */
#endif


/* Assembly helpers */
#define DMB() __asm__ volatile ("dmb")
Expand All @@ -38,10 +52,14 @@ void sleep_us(unsigned int us);
#define PSEL_PORT(n) (((n) & 0x1) << 5)

/* Non-volatile memory controller */
#ifdef TZEN
#define NVMC_BASE (0x50039000)
#ifdef TARGET_nrf5340_APP
#ifdef TZEN
#define NVMC_BASE (0x50039000)
#else
#define NVMC_BASE (0x40039000)
#endif
#else
#define NVMC_BASE (0x40039000)
#define NVMC_BASE (0x41080000)
#endif
#define NVMC_READY *((volatile uint32_t *)(NVMC_BASE + 0x400))
#define NVMC_READYNEXT *((volatile uint32_t *)(NVMC_BASE + 0x408))
Expand All @@ -60,48 +78,52 @@ void sleep_us(unsigned int us);
#define FLASH_PAGE_SIZE (4096)

/* Clock control */
#ifdef TZEN
#define CLOCK_BASE_APP (0x50005000)
#ifdef TARGET_nrf5340_APP
#ifdef TZEN
#define CLOCK_BASE (0x50005000)
#else
#define CLOCK_BASE (0x40005000)
#endif
#else
#define CLOCK_BASE_APP (0x40005000)
#define CLOCK_BASE (0x41005000) /* network core */
#endif
#define CLOCK_BASE_NET (0x41005000) /* network core */
#define CLOCK_HFCLKSTART *((volatile uint32_t *)(CLOCK_BASE_APP + 0x000))
#define CLOCK_HFCLKSTOP *((volatile uint32_t *)(CLOCK_BASE_APP + 0x004))
#define CLOCK_HFCLKSTARTED *((volatile uint32_t *)(CLOCK_BASE_APP + 0x100))
#define CLOCK_HFCLKSTAT *((volatile uint32_t *)(CLOCK_BASE_APP + 0x40C))
#define CLOCK_HFCLKSRC *((volatile uint32_t *)(CLOCK_BASE_APP + 0x514))
#define CLOCK_HFCLKSTART *((volatile uint32_t *)(CLOCK_BASE + 0x000))
#define CLOCK_HFCLKSTOP *((volatile uint32_t *)(CLOCK_BASE + 0x004))
#define CLOCK_HFCLKSTARTED *((volatile uint32_t *)(CLOCK_BASE + 0x100))
#define CLOCK_HFCLKSTAT *((volatile uint32_t *)(CLOCK_BASE + 0x40C))
#define CLOCK_HFCLKSRC *((volatile uint32_t *)(CLOCK_BASE + 0x514))
#define CLOCK_HFCLKSRC_HFXO 1
#define CLOCK_HFCLKCTRL *((volatile uint32_t *)(CLOCK_BASE_APP + 0x558))
#define CLOCK_HFCLKCTRL *((volatile uint32_t *)(CLOCK_BASE + 0x558))
#define CLOCK_HFCLKCTRL_DIV1 0
#define CLOCK_HFCLKCTRL_DIV2 1

/* Used by QSPI */
#define CLOCK_HFCLK192MSTART *((volatile uint32_t *)(CLOCK_BASE_APP + 0x020))
#define CLOCK_HFCLK192MSTOP *((volatile uint32_t *)(CLOCK_BASE_APP + 0x024))
#define CLOCK_HFCLK192MSTARTED *((volatile uint32_t *)(CLOCK_BASE_APP + 0x124))
#define CLOCK_HFCLK192MSRC *((volatile uint32_t *)(CLOCK_BASE_APP + 0x580))
#define CLOCK_HFCLK192MSTART *((volatile uint32_t *)(CLOCK_BASE + 0x020))
#define CLOCK_HFCLK192MSTOP *((volatile uint32_t *)(CLOCK_BASE + 0x024))
#define CLOCK_HFCLK192MSTARTED *((volatile uint32_t *)(CLOCK_BASE + 0x124))
#define CLOCK_HFCLK192MSRC *((volatile uint32_t *)(CLOCK_BASE + 0x580))
#define CLOCK_HFCLK192MSRC_HFXO 1
#define CLOCK_HFCLK192MCTRL *((volatile uint32_t *)(CLOCK_BASE_APP + 0x5B8))
#define CLOCK_HFCLK192MCTRL *((volatile uint32_t *)(CLOCK_BASE + 0x5B8))
#define CLOCK_HFCLK192MCTRL_DIV1 0
#define CLOCK_HFCLK192MCTRL_DIV2 1
#define CLOCK_HFCLK192MCTRL_DIV4 2



/* GPIO Port (0-1) */
#ifdef TZEN
#define GPIO_BASE_APP(n) (0x50842500 + (((n) & 0x1) * 0x300))
#ifdef TARGET_nrf5340_APP
#ifdef TZEN
#define GPIO_BASE(n) (0x50842500 + (((n) & 0x1) * 0x300))
#else
#define GPIO_BASE(n) (0x40842500 + (((n) & 0x1) * 0x300))
#endif
#else
#define GPIO_BASE_APP(n) (0x40842500 + (((n) & 0x1) * 0x300))
#define GPIO_BASE(n) (0x418C0500 + (((n) & 0x1) * 0x300))
#endif
#define GPIO_BASE_NET(n) (0x418C0500 + (((n) & 0x1) * 0x300))
#define GPIO_OUT(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x004))
#define GPIO_OUTSET(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x008))
#define GPIO_OUTCLR(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x00C))
#define GPIO_IN(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x010))
#define GPIO_DIRSET(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x018))
#define GPIO_PIN_CNF(n,p) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x200 + ((p) * 0x4)))
#define GPIO_OUT(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x004))
#define GPIO_OUTSET(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x008))
#define GPIO_OUTCLR(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x00C))
#define GPIO_IN(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x010))
#define GPIO_DIRSET(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x018))
#define GPIO_PIN_CNF(n,p) *((volatile uint32_t *)(GPIO_BASE(n) + 0x200 + ((p) * 0x4)))

#define GPIO_CNF_IN 0
#define GPIO_CNF_IN_DIS 2
Expand All @@ -115,10 +137,15 @@ void sleep_us(unsigned int us);
#define GPIO_CNF_MCUSEL(n) (((n) & 0x7) << 28)

/* UART (0-1) */
#ifdef TZEN
#define UART_BASE(n) (0x50008000 + (((n) & 0x1) * 0x1000))
#ifdef TARGET_nrf5340_APP
#ifdef TZEN
#define UART_BASE(n) (0x50008000 + (((n) & 0x1) * 0x1000))
#else
#define UART_BASE(n) (0x40008000 + (((n) & 0x1) * 0x1000))
#endif
#else
#define UART_BASE(n) (0x40008000 + (((n) & 0x1) * 0x1000))
#define UART_BASE(n) (0x41013000) /* only UARTE0 */

#endif
#define UART_TASK_STARTTX(n) *((volatile uint32_t *)(UART_BASE(n) + 0x008))
#define UART_TASK_STOPTX(n) *((volatile uint32_t *)(UART_BASE(n) + 0x00C))
Expand All @@ -136,10 +163,14 @@ void sleep_us(unsigned int us);
void uart_write_sz(const char* c, unsigned int sz);

/* SPI (0-2) */
#ifdef TZEN
#define SPI_BASE(n) (0x50008000 + (((n) & 0x3) * 0x1000))
#ifdef TARGET_nrf5340_APP
#ifdef TZEN
#define SPI_BASE(n) (0x50008000 + (((n) & 0x3) * 0x1000))
#else
#define SPI_BASE(n) (0x40008000 + (((n) & 0x3) * 0x1000))
#endif
#else
#define SPI_BASE(n) (0x40008000 + (((n) & 0x3) * 0x1000))
#define SPI_BASE(n) (0x41013000) /* SPIM0 only */
#endif
#define SPI_TASKS_START(n) *((volatile uint32_t *)(SPI_BASE(n) + 0x010))
#define SPI_TASKS_STOP(n) *((volatile uint32_t *)(SPI_BASE(n) + 0x014))
Expand Down Expand Up @@ -169,80 +200,100 @@ void uart_write_sz(const char* c, unsigned int sz);
#define SPI_FREQ_M32 0x14000000

/* QSPI */
#ifdef TZEN
#define QSPI_BASE (0x5002B000)
#ifdef TARGET_nrf5340_APP
#ifdef TZEN
#define QSPI_BASE (0x5002B000)
#else
#define QSPI_BASE (0x4002B000)
#endif
#define QSPI_TASKS_ACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x000))
#define QSPI_TASKS_READSTART *((volatile uint32_t *)(QSPI_BASE + 0x004))
#define QSPI_TASKS_WRITESTART *((volatile uint32_t *)(QSPI_BASE + 0x008))
#define QSPI_TASKS_ERASESTART *((volatile uint32_t *)(QSPI_BASE + 0x00C))
#define QSPI_TASKS_DEACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x010))
#define QSPI_EVENTS_READY *((volatile uint32_t *)(QSPI_BASE + 0x100))

#define QSPI_INTEN *((volatile uint32_t *)(QSPI_BASE + 0x300))
#define QSPI_INTENSET *((volatile uint32_t *)(QSPI_BASE + 0x304))
#define QSPI_INTENCLR *((volatile uint32_t *)(QSPI_BASE + 0x308))

#define QSPI_ENABLE *((volatile uint32_t *)(QSPI_BASE + 0x500))

#define QSPI_READ_SRC *((volatile uint32_t *)(QSPI_BASE + 0x504))
#define QSPI_READ_DST *((volatile uint32_t *)(QSPI_BASE + 0x508))
#define QSPI_READ_CNT *((volatile uint32_t *)(QSPI_BASE + 0x50C))
#define QSPI_WRITE_DST *((volatile uint32_t *)(QSPI_BASE + 0x510))
#define QSPI_WRITE_SRC *((volatile uint32_t *)(QSPI_BASE + 0x514))
#define QSPI_WRITE_CNT *((volatile uint32_t *)(QSPI_BASE + 0x518))
#define QSPI_ERASE_PTR *((volatile uint32_t *)(QSPI_BASE + 0x51C))
#define QSPI_ERASE_LEN *((volatile uint32_t *)(QSPI_BASE + 0x520))

#define QSPI_PSEL_SCK *((volatile uint32_t *)(QSPI_BASE + 0x524))
#define QSPI_PSEL_CSN *((volatile uint32_t *)(QSPI_BASE + 0x528))
#define QSPI_PSEL_IO0 *((volatile uint32_t *)(QSPI_BASE + 0x530))
#define QSPI_PSEL_IO1 *((volatile uint32_t *)(QSPI_BASE + 0x534))
#define QSPI_PSEL_IO2 *((volatile uint32_t *)(QSPI_BASE + 0x538))
#define QSPI_PSEL_IO3 *((volatile uint32_t *)(QSPI_BASE + 0x53C))

#define QSPI_IFCONFIG0 *((volatile uint32_t *)(QSPI_BASE + 0x544))
#define QSPI_IFCONFIG1 *((volatile uint32_t *)(QSPI_BASE + 0x600))

#define QSPI_STATUS *((volatile uint32_t *)(QSPI_BASE + 0x604))
#define QSPI_ADDRCONF *((volatile uint32_t *)(QSPI_BASE + 0x624))
#define QSPI_CINSTRCONF *((volatile uint32_t *)(QSPI_BASE + 0x634))
#define QSPI_CINSTRDAT0 *((volatile uint32_t *)(QSPI_BASE + 0x638))
#define QSPI_CINSTRDAT1 *((volatile uint32_t *)(QSPI_BASE + 0x63C))
#define QSPI_IFTIMING *((volatile uint32_t *)(QSPI_BASE + 0x640))

#define QSPI_IFCONFIG0_READOC_MASK 0x7
#define QSPI_IFCONFIG0_READOC_FASTREAD (0) /* opcode 0x0B */
#define QSPI_IFCONFIG0_READOC_READ2O (1) /* opcode 0x3B */
#define QSPI_IFCONFIG0_READOC_READ2IO (2) /* opcode 0xBB */
#define QSPI_IFCONFIG0_READOC_READ4O (3) /* opcode 0x6B */
#define QSPI_IFCONFIG0_READOC_READ4IO (4) /* opcode 0xEB */
#define QSPI_IFCONFIG0_WRITEOC_MASK ((0x7) << 3)
#define QSPI_IFCONFIG0_WRITEOC_PP ((0) << 3) /* opcode 0x02 */
#define QSPI_IFCONFIG0_WRITEOC_PP2O ((1) << 3) /* opcode 0xA2 */
#define QSPI_IFCONFIG0_WRITEOC_PP4O ((2) << 3) /* opcode 0x32 */
#define QSPI_IFCONFIG0_WRITEOC_PP4IO ((3) << 3) /* opcode 0x38 */
#define QSPI_IFCONFIG0_ADDRMODE_24BIT ((0) << 6)
#define QSPI_IFCONFIG0_ADDRMODE_32BIT ((1) << 6)
#define QSPI_IFCONFIG0_DPMENABLE ((1) << 7)
#define QSPI_IFCONFIG0_PPSIZE_256 ((0) << 12)
#define QSPI_IFCONFIG0_PPSIZE_512 ((1) << 12)

#define QSPI_IFCONFIG1_SCKDELAY_MASK 0xFF
#define QSPI_IFCONFIG1_SCKDELAY(n) ((n) & QSPI_IFCONFIG1_SCKDELAY_MASK)
#define QSPI_IFCONFIG1_SPIMODE0 0
#define QSPI_IFCONFIG1_SPIMODE3 (1UL << 25)
#define QSPI_IFCONFIG1_SCKFREQ_MASK ((0xF) << 28)
#define QSPI_IFCONFIG1_SCKFREQ(n) (((n) & 0xF) << 28)

#define QSPI_CINSTRCONF_OPCODE(n) ((n) & 0xFF)
#define QSPI_CINSTRCONF_LENGTH(n) (((n) & 0xF) << 8)
#define QSPI_CINSTRCONF_LIO2 (1 << 12)
#define QSPI_CINSTRCONF_LIO3 (1 << 13)
#define QSPI_CINSTRCONF_WREN (1 << 15) /* send WREN opcode 0x6 before */

#define QSPI_IFTIMING_RXDELAY(n) (((n) & 0x7) << 8)
#endif

/* interprocessor communication (IPC) peripheral */
#ifdef TARGET_nrf5340_APP
#ifdef TZEN
#define IPC_BASE (0x5002A000)
#else
#define IPC_BASE (0x4002A000)
#endif
#else
#define QSPI_BASE (0x4002B000)
#define IPC_BASE (0x4002A000) /* network core */
#endif
#define QSPI_TASKS_ACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x000))
#define QSPI_TASKS_READSTART *((volatile uint32_t *)(QSPI_BASE + 0x004))
#define QSPI_TASKS_WRITESTART *((volatile uint32_t *)(QSPI_BASE + 0x008))
#define QSPI_TASKS_ERASESTART *((volatile uint32_t *)(QSPI_BASE + 0x00C))
#define QSPI_TASKS_DEACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x010))
#define QSPI_EVENTS_READY *((volatile uint32_t *)(QSPI_BASE + 0x100))

#define QSPI_INTEN *((volatile uint32_t *)(QSPI_BASE + 0x300))
#define QSPI_INTENSET *((volatile uint32_t *)(QSPI_BASE + 0x304))
#define QSPI_INTENCLR *((volatile uint32_t *)(QSPI_BASE + 0x308))

#define QSPI_ENABLE *((volatile uint32_t *)(QSPI_BASE + 0x500))

#define QSPI_READ_SRC *((volatile uint32_t *)(QSPI_BASE + 0x504))
#define QSPI_READ_DST *((volatile uint32_t *)(QSPI_BASE + 0x508))
#define QSPI_READ_CNT *((volatile uint32_t *)(QSPI_BASE + 0x50C))
#define QSPI_WRITE_DST *((volatile uint32_t *)(QSPI_BASE + 0x510))
#define QSPI_WRITE_SRC *((volatile uint32_t *)(QSPI_BASE + 0x514))
#define QSPI_WRITE_CNT *((volatile uint32_t *)(QSPI_BASE + 0x518))
#define QSPI_ERASE_PTR *((volatile uint32_t *)(QSPI_BASE + 0x51C))
#define QSPI_ERASE_LEN *((volatile uint32_t *)(QSPI_BASE + 0x520))

#define QSPI_PSEL_SCK *((volatile uint32_t *)(QSPI_BASE + 0x524))
#define QSPI_PSEL_CSN *((volatile uint32_t *)(QSPI_BASE + 0x528))
#define QSPI_PSEL_IO0 *((volatile uint32_t *)(QSPI_BASE + 0x530))
#define QSPI_PSEL_IO1 *((volatile uint32_t *)(QSPI_BASE + 0x534))
#define QSPI_PSEL_IO2 *((volatile uint32_t *)(QSPI_BASE + 0x538))
#define QSPI_PSEL_IO3 *((volatile uint32_t *)(QSPI_BASE + 0x53C))

#define QSPI_IFCONFIG0 *((volatile uint32_t *)(QSPI_BASE + 0x544))
#define QSPI_IFCONFIG1 *((volatile uint32_t *)(QSPI_BASE + 0x600))

#define QSPI_STATUS *((volatile uint32_t *)(QSPI_BASE + 0x604))
#define QSPI_ADDRCONF *((volatile uint32_t *)(QSPI_BASE + 0x624))
#define QSPI_CINSTRCONF *((volatile uint32_t *)(QSPI_BASE + 0x634))
#define QSPI_CINSTRDAT0 *((volatile uint32_t *)(QSPI_BASE + 0x638))
#define QSPI_CINSTRDAT1 *((volatile uint32_t *)(QSPI_BASE + 0x63C))
#define QSPI_IFTIMING *((volatile uint32_t *)(QSPI_BASE + 0x640))

#define QSPI_IFCONFIG0_READOC_MASK 0x7
#define QSPI_IFCONFIG0_READOC_FASTREAD (0) /* opcode 0x0B */
#define QSPI_IFCONFIG0_READOC_READ2O (1) /* opcode 0x3B */
#define QSPI_IFCONFIG0_READOC_READ2IO (2) /* opcode 0xBB */
#define QSPI_IFCONFIG0_READOC_READ4O (3) /* opcode 0x6B */
#define QSPI_IFCONFIG0_READOC_READ4IO (4) /* opcode 0xEB */
#define QSPI_IFCONFIG0_WRITEOC_MASK ((0x7) << 3)
#define QSPI_IFCONFIG0_WRITEOC_PP ((0) << 3) /* opcode 0x02 */
#define QSPI_IFCONFIG0_WRITEOC_PP2O ((1) << 3) /* opcode 0xA2 */
#define QSPI_IFCONFIG0_WRITEOC_PP4O ((2) << 3) /* opcode 0x32 */
#define QSPI_IFCONFIG0_WRITEOC_PP4IO ((3) << 3) /* opcode 0x38 */
#define QSPI_IFCONFIG0_ADDRMODE_24BIT ((0) << 6)
#define QSPI_IFCONFIG0_ADDRMODE_32BIT ((1) << 6)
#define QSPI_IFCONFIG0_DPMENABLE ((1) << 7)
#define QSPI_IFCONFIG0_PPSIZE_256 ((0) << 12)
#define QSPI_IFCONFIG0_PPSIZE_512 ((1) << 12)

#define QSPI_IFCONFIG1_SCKDELAY_MASK 0xFF
#define QSPI_IFCONFIG1_SCKDELAY(n) ((n) & QSPI_IFCONFIG1_SCKDELAY_MASK)
#define QSPI_IFCONFIG1_SPIMODE0 0
#define QSPI_IFCONFIG1_SPIMODE3 (1UL << 25)
#define QSPI_IFCONFIG1_SCKFREQ_MASK ((0xF) << 28)
#define QSPI_IFCONFIG1_SCKFREQ(n) (((n) & 0xF) << 28)

#define QSPI_CINSTRCONF_OPCODE(n) ((n) & 0xFF)
#define QSPI_CINSTRCONF_LENGTH(n) (((n) & 0xF) << 8)
#define QSPI_CINSTRCONF_LIO2 (1 << 12)
#define QSPI_CINSTRCONF_LIO3 (1 << 13)
#define QSPI_CINSTRCONF_WREN (1 << 15) /* send WREN opcode 0x6 before */

#define QSPI_IFTIMING_RXDELAY(n) (((n) & 0x7) << 8)
#define IPC_TASKS_SEND(n) *((volatile uint32_t *)(IPC_BASE + 0x000 + (((n) & 0xF) * 0x4)))
#define IPC_SUBSCRIBE_SEND(n) *((volatile uint32_t *)(IPC_BASE + 0x080 + (((n) & 0xF) * 0x4)))
#define IPC_EVENTS_RECEIVE(n) *((volatile uint32_t *)(IPC_BASE + 0x100 + (((n) & 0xF) * 0x4)))
#define IPC_PUBLISH_RECEIVE(n) *((volatile uint32_t *)(IPC_BASE + 0x180 + (((n) & 0xF) * 0x4)))
#define IPC_SEND_CNF(n) *((volatile uint32_t *)(IPC_BASE + 0x510 + (((n) & 0xF) * 0x4)))
#define IPC_RECEIVE_CNF(n) *((volatile uint32_t *)(IPC_BASE + 0x590 + (((n) & 0xF) * 0x4)))
#define IPC_GPMEM(n) *((volatile uint32_t *)(IPC_BASE + 0x610 + (((n) & 0x1) * 0x4)))

#endif /* !_HAL_NRF5340_H_ */
4 changes: 4 additions & 0 deletions options.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -852,3 +852,7 @@ ifneq ($(KEYVAULT_MAX_ITEMS),)
CFLAGS+=-DKEYVAULT_MAX_ITEMS=$(KEYVAULT_MAX_ITEMS)
endif


ifneq ($(CORE),)
CFLAGS+=-DCORE=$(CORE)
endif

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