Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

i#3544 RV64: Preserve vtype and vl vector registers #7110

Merged
merged 15 commits into from
Dec 19, 2024
Merged

i#3544 RV64: Preserve vtype and vl vector registers #7110

Show file tree
Hide file tree
Changes from 13 commits
Commits
Show all changes
15 commits
Select commit Hold shift + click to select a range
6c8f181
Add saving and restoring the vtype and vl vector registers for RISC-V…
mariospaok4 Dec 9, 2024
7bc9eff
Fixed identation
mariospaok4 Dec 9, 2024
2410e00
Removed trailing spaces
mariospaok4 Dec 9, 2024
e219785
Split long lines of code in two
mariospaok4 Dec 9, 2024
870f65c
Fixed formating
mariospaok4 Dec 9, 2024
fbf3b85
More fixed formating
mariospaok4 Dec 9, 2024
e3b159b
Merge branch 'master' into master
mariospaok4 Dec 10, 2024
484d33f
Merge branch 'master' into master
mariospaok4 Dec 10, 2024
b47f3ce
Merge branch 'master' into master
mariospaok4 Dec 16, 2024
c5fca47
i#3544 RV64: Preserve vtype and vl vector registers
mariospaok4 Dec 17, 2024
ac62273
Merge branch 'master' into master
mariospaok4 Dec 17, 2024
899bf1c
Merge branch 'master' into master
mariospaok4 Dec 18, 2024
549fb3d
i#3544 RV64: Preserve vtype and vl vector registers
mariospaok4 Dec 18, 2024
1a5e921
i#3544 RV64: Preserve vtype and vl vector registers
mariospaok4 Dec 18, 2024
8d72b0d
Merge branch 'master' into master
mariospaok4 Dec 19, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions core/arch/arch.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -176,6 +176,8 @@ mixed_mode_enabled(void)
# define XFLAGS_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, fcsr)))
mariospaok4 marked this conversation as resolved.
Show resolved Hide resolved
mariospaok4 marked this conversation as resolved.
Show resolved Hide resolved
# define VSTART_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vstart)))
# define VCSR_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vcsr)))
# define VL_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vl)))
# define VTYPE_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, vtype)))
# define SCRATCH_REG0 DR_REG_A0
# define SCRATCH_REG1 DR_REG_A1
# define SCRATCH_REG2 DR_REG_A2
Expand Down
2 changes: 1 addition & 1 deletion core/arch/emit_utils_shared.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4980,8 +4980,8 @@ emit_fcache_enter_gonative(dcontext_t *dcontext, generated_code_t *code, byte *p
append_call_exit_dr_hook(dcontext, &ilist, absolute, shared);

/* restore the original register state */
append_restore_xflags(dcontext, &ilist, absolute);
append_restore_simd_reg(dcontext, &ilist, absolute);
append_restore_xflags(dcontext, &ilist, absolute);
mariospaok4 marked this conversation as resolved.
Show resolved Hide resolved
append_restore_gpr(dcontext, &ilist, absolute);

/* We need to restore the stolen reg, but we have no scratch registers.
Expand Down
20 changes: 20 additions & 0 deletions core/arch/riscv64/emit_utils.c
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/* **********************************************************
* Copyright (c) 2022 Rivos, Inc. All rights reserved.
* Copyright (c) 2024 Foundation of Research and Technology, Hellas.
* **********************************************************/

/*
Expand Down Expand Up @@ -54,6 +55,8 @@
#define FCSR 0x003
#define VSTART 0x008
#define VCSR 0x00F
#define VL 0xC20
#define VTYPE 0xC21
mariospaok4 marked this conversation as resolved.
Show resolved Hide resolved

/* Instruction fixed bits constants. */

Expand Down Expand Up @@ -661,6 +664,12 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
INSTR_CREATE_csrrw(dcontext, opnd_create_reg(DR_REG_ZERO),
opnd_create_reg(DR_REG_A0),
opnd_create_immed_int(VCSR, OPSZ_12b)));

APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A0, VL_OFFSET));
APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A1, VTYPE_OFFSET));
APP(ilist,
INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0),
opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)));
}
}

Expand Down Expand Up @@ -877,6 +886,17 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute
opnd_create_reg(DR_REG_ZERO),
opnd_create_immed_int(VCSR, OPSZ_12b)));
APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VCSR_OFFSET));

APP(ilist,
INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1),
opnd_create_reg(DR_REG_ZERO),
opnd_create_immed_int(VL, OPSZ_12b)));
APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VL_OFFSET));
APP(ilist,
INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1),
opnd_create_reg(DR_REG_ZERO),
opnd_create_immed_int(VTYPE, OPSZ_12b)));
APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET));
}
}

Expand Down
48 changes: 48 additions & 0 deletions core/arch/riscv64/mangle.c
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/* **********************************************************
* Copyright (c) 2022 Rivos, Inc. All rights reserved.
* Copyright (c) 2024 Foundation of Research and Technology, Hellas.
* **********************************************************/

/*
Expand Down Expand Up @@ -45,6 +46,8 @@
#define FCSR 0x003
#define VSTART 0x008
#define VCSR 0x00F
#define VL 0xC20
#define VTYPE 0xC21

/* TODO i#3544: Think of a better way to represent these fields in the IR. */
/* Volume I: RISC-V Unprivileged ISA V20191213.
Expand Down Expand Up @@ -192,6 +195,32 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,

dstack_offs += XSP_SZ;

if (proc_has_feature(FEATURE_VECTOR)) {
PRE(ilist, instr,
INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
opnd_create_reg(DR_REG_ZERO),
opnd_create_immed_int(VL, OPSZ_12b)));

PRE(ilist, instr,
INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),
opnd_create_reg(DR_REG_A0)));
}

dstack_offs += XSP_SZ;

if (proc_has_feature(FEATURE_VECTOR)) {
PRE(ilist, instr,
INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
opnd_create_reg(DR_REG_ZERO),
opnd_create_immed_int(VTYPE, OPSZ_12b)));

PRE(ilist, instr,
INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),
opnd_create_reg(DR_REG_A0)));
}

dstack_offs += 2 * XSP_SZ;

/* Push vector registers. */
if (proc_has_feature(FEATURE_VECTOR)) {
/* ma: mask agnostic
Expand Down Expand Up @@ -309,6 +338,25 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist
opnd_create_reg(DR_REG_SP),
opnd_create_immed_int(DR_NUM_FPR_REGS * XSP_SZ, OPSZ_12b)));

current_offs -= 2 * XSP_SZ;

/* Uses c.[f]ldsp for some reason beyond my comprehension, same below. */
if (proc_has_feature(FEATURE_VECTOR)) {
PRE(ilist, instr,
INSTR_CREATE_c_ldsp(
dcontext, opnd_create_reg(DR_REG_A0),
OPND_CREATE_MEM64(DR_REG_SP, current_offs - DR_NUM_FPR_REGS * XSP_SZ)));
PRE(ilist, instr,
INSTR_CREATE_c_ldsp(
dcontext, opnd_create_reg(DR_REG_A1),
OPND_CREATE_MEM64(DR_REG_SP,
current_offs + XSP_SZ - DR_NUM_FPR_REGS * XSP_SZ)));
/* vsetvl a0, a0, a1 */
PRE(ilist, instr,
INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0),
opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)));
}

/* Uses c.[f]ldsp to save space, same below. */
current_offs -= XSP_SZ;

Expand Down
4 changes: 2 additions & 2 deletions core/arch/riscv64/riscv64.asm
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ START_FILE

/* sizeof(priv_mcontext_t) rounded up to a multiple of 16 */
/* The reserved space for SIMD is also included. */
#define PRIV_MCONTEXT_SIZE 0x620
#define PRIV_MCONTEXT_SIZE 0x630

/* offset of priv_mcontext_t in dr_mcontext_t */
#define PRIV_MCONTEXT_OFFSET 16
Expand All @@ -52,7 +52,7 @@ START_FILE
#endif

/* offsetof(dcontext_t, dstack) */
#define dstack_OFFSET 0x668
#define dstack_OFFSET 0x678
/* offsetof(dcontext_t, is_exiting) */
#define is_exiting_OFFSET (dstack_OFFSET + 1 * ARG_SZ)

Expand Down
2 changes: 2 additions & 0 deletions core/lib/mcxtx_api.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -566,6 +566,8 @@
reg_t fcsr; /**< Floating-Point Control Register. */
reg_t vstart; /**< Vector Start Index CSR. */
reg_t vcsr; /**< Vector Control and Status Register. */
reg_t vl; /**< Vector Length Register. */
reg_t vtype; /**< Vector Type Register. */
/** The Vector registers. */
dr_simd_t simd[MCXT_NUM_SIMD_SLOTS];
#else /* RISCV64 */
Expand Down
Loading