DMA SG delayed input

library/utilities/test_harness_system_bd.tcl

@@ -198,4 +198,4 @@ ad_connect irq axi_intc/irq
 set DDR_BASE 0x80000000
 create_bd_addr_seg -range ${DDR_BASE} -offset ${DDR_BASE} [get_bd_addr_spaces /mng_axi_vip/Master_AXI] \
   [get_bd_addr_segs ddr_axi_vip/S_AXI/Reg] SEG_mng_ddr_cntlr
-adi_sim_add_define "DDR_BA=[format "%d" ${DDR_BASE}]"
+adi_sim_add_define "DDR_BA='h[format "%X" ${DDR_BASE}]"

testbenches/ip/dma_sg_2/Makefile

@@ -0,0 +1,63 @@
+####################################################################################
+####################################################################################
+## Copyright 2022(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += ../../../library/utilities/utils.svh
+SV_DEPS += ../../../library/utilities/logger_pkg.sv
+SV_DEPS += ../../../library/regmaps/reg_accessor.sv
+SV_DEPS += ../../../library/vip/amd/m_axis_sequencer.sv
+SV_DEPS += ../../../library/vip/amd/s_axis_sequencer.sv
+SV_DEPS += ../../../library/vip/amd/m_axi_sequencer.sv
+SV_DEPS += ../../../library/vip/amd/s_axi_sequencer.sv
+SV_DEPS += ../../../library/utilities/test_harness_env.sv
+SV_DEPS += ../../../library/regmaps/adi_peripheral_pkg.sv
+SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv
+SV_DEPS += ../../../library/drivers/common/mailbox.sv
+SV_DEPS += ../../../library/drivers/common/x_monitor.sv
+SV_DEPS += ../../../library/drivers/common/scoreboard.sv
+SV_DEPS += ../../../library/drivers/dmac/dmac_api.sv
+SV_DEPS += ../../../library/drivers/dmac/dma_trans.sv
+SV_DEPS += ../../../library/regmaps/adi_regmap_dmac_pkg.sv
+SV_DEPS += environment.sv
+SV_DEPS += system_tb.sv
+
+ENV_DEPS += system_project.tcl
+ENV_DEPS += system_bd.tcl
+ENV_DEPS += ../../../scripts/adi_sim.tcl
+ENV_DEPS += ../../../scripts/run_sim.tcl
+
+LIB_DEPS := util_cdc
+LIB_DEPS += util_axis_fifo
+LIB_DEPS += axi_dmac
+
+# default test program
+TP := test_program
+
+# config files should have the following format
+#  cfg_<param1>_<param2>.tcl
+CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
+#$(warning $(CFG_FILES))
+
+# List of tests and configuration combinations that has to be run
+# Format is:  <configuration>:<test name>
+TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
+#TESTS += cfg1_mm2mm_default:directed_test
+#TESTS += cfg1:test_program
+#TESTS += cfg2_fsync:test_program
+#TESTS += cfg2_fsync:test_frame_delay
+
+include ../../../scripts/project-sim.mk
+
+# usage :
+#
+# run specific test on a specific configuration in gui mode
+# 	make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
+#
+# run all test from a configuration
+# 	make cfg1_mm2mm_default
+
+####################################################################################
+####################################################################################

testbenches/ip/dma_sg_2/README.md

@@ -0,0 +1,27 @@
+Usage :
+
+Run all tests in batch mode:
+
+	make
+
+
+Run all tests in GUI mode:
+
+	make MODE=gui
+
+
+Run specific test on a specific configuration in gui mode:
+
+	make CFG=<name of cfg> TST=<name of test> MODE=gui
+
+
+Run all test from a configuration:
+
+	make <name of cfg>
+
+
+Where:
+
+ * <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
+ * <name of test> is a file from the tests directory without the tcl extension
+

testbenches/ip/dma_sg_2/cfgs/cfg1.tcl

@@ -0,0 +1,19 @@
+global ad_project_params
+
+set ad_project_params(ADC_DATA_PATH_WIDTH)  16     ; ##
+set ad_project_params(DAC_DATA_PATH_WIDTH)  16     ; ##
+
+set ad_project_params(ADC_PATH_TYPE) 0             ; ## RX
+set ad_project_params(ADC_OFFLOAD_MEM_TYPE) 0      ; ## External storage
+set ad_project_params(ADC_OFFLOAD_SIZE) 2048       ; ## Storage size in bytes
+set ad_project_params(ADC_OFFLOAD_SRC_DWIDTH) 128  ; ## Source data width
+set ad_project_params(ADC_OFFLOAD_DST_DWIDTH) 128  ; ## Destination data width
+
+set ad_project_params(DAC_PATH_TYPE) 0             ; ## TX
+set ad_project_params(DAC_OFFLOAD_MEM_TYPE) 0      ; ## External storage
+set ad_project_params(DAC_OFFLOAD_SIZE) 2048       ; ## Storage size in bytes
+set ad_project_params(DAC_OFFLOAD_SRC_DWIDTH) 128  ; ## Source data width
+set ad_project_params(DAC_OFFLOAD_DST_DWIDTH) 128  ; ## Destination data width
+
+set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512      ; ## PLDDR's AXI4 interface data width
+

testbenches/ip/dma_sg_2/environment.sv

@@ -0,0 +1,191 @@
+`include "utils.svh"
+
+package environment_pkg;
+
+  import m_axi_sequencer_pkg::*;
+  import s_axi_sequencer_pkg::*;
+  import m_axis_sequencer_pkg::*;
+  import s_axis_sequencer_pkg::*;
+  import logger_pkg::*;
+
+  import axi_vip_pkg::*;
+  import axi4stream_vip_pkg::*;
+  import test_harness_env_pkg::*;
+  import scoreboard_pkg::*;
+  import x_monitor_pkg::*;
+
+  import `PKGIFY(test_harness, mng_axi_vip)::*;
+  import `PKGIFY(test_harness, ddr_axi_vip)::*;
+
+  import `PKGIFY(test_harness, adc_src_axis)::*;
+  import `PKGIFY(test_harness, dac_dst_axis)::*;
+  import `PKGIFY(test_harness, adc_dst_axi_pt)::*;
+  import `PKGIFY(test_harness, dac_src_axi_pt)::*;
+
+  class environment extends test_harness_env;
+
+    // agents and sequencers
+    `AGENT(test_harness, adc_src_axis, mst_t) adc_src_axis_agent;
+    `AGENT(test_harness, dac_dst_axis, slv_t) dac_dst_axis_agent;
+    `AGENT(test_harness, adc_dst_axi_pt, passthrough_mem_t) adc_dst_axi_pt_agent;
+    `AGENT(test_harness, dac_src_axi_pt, passthrough_mem_t) dac_src_axi_pt_agent;
+
+    m_axis_sequencer #(`AGENT(test_harness, adc_src_axis, mst_t),
+                      `AXIS_VIP_PARAMS(test_harness, adc_src_axis)
+                      ) adc_src_axis_seq;
+    s_axis_sequencer #(`AGENT(test_harness, dac_dst_axis, slv_t)) dac_dst_axis_seq;
+    s_axi_sequencer #(`AGENT(test_harness, adc_dst_axi_pt, passthrough_mem_t)) adc_dst_axi_pt_seq;
+    s_axi_sequencer #(`AGENT(test_harness, dac_src_axi_pt, passthrough_mem_t)) dac_src_axi_pt_seq;
+
+    x_axis_monitor #(`AGENT(test_harness, adc_src_axis, mst_t)) adc_src_axis_mon;
+    x_axis_monitor #(`AGENT(test_harness, dac_dst_axis, slv_t)) dac_dst_axis_mon;
+    x_axi_monitor #(`AGENT(test_harness, adc_dst_axi_pt, passthrough_mem_t), WRITE_OP) adc_dst_axi_pt_mon;
+    x_axi_monitor #(`AGENT(test_harness, dac_src_axi_pt, passthrough_mem_t), READ_OP) dac_src_axi_pt_mon;
+
+    scoreboard scoreboard_tx;
+    scoreboard scoreboard_rx;
+
+    //============================================================================
+    // Constructor
+    //============================================================================
+    function new (
+      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if,
+      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if,
+      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if,
+
+      virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if,
+
+      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if,
+      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if,
+
+      virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, adc_src_axis)) adc_src_axis_vip_if,
+      virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dac_dst_axis)) dac_dst_axis_vip_if,
+      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, adc_dst_axi_pt)) adc_dst_axi_pt_vip_if,
+      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, dac_src_axi_pt)) dac_src_axi_pt_vip_if
+    );
+
+      // creating the agents
+      super.new(sys_clk_vip_if, 
+                dma_clk_vip_if, 
+                ddr_clk_vip_if, 
+                sys_rst_vip_if, 
+                mng_vip_if, 
+                ddr_vip_if);
+
+      adc_src_axis_agent = new("ADC Source AXI Stream Agent", adc_src_axis_vip_if);
+      dac_dst_axis_agent = new("DAC Destination AXI Stream Agent", dac_dst_axis_vip_if);
+      adc_dst_axi_pt_agent = new("ADC Destination AXI Agent", adc_dst_axi_pt_vip_if);
+      dac_src_axi_pt_agent = new("DAC Source AXI Agent", dac_src_axi_pt_vip_if);
+
+      adc_src_axis_seq = new(adc_src_axis_agent);
+      dac_dst_axis_seq = new(dac_dst_axis_agent);
+      adc_dst_axi_pt_seq = new(adc_dst_axi_pt_agent);
+      dac_src_axi_pt_seq = new(dac_src_axi_pt_agent);
+
+      adc_src_axis_mon = new("ADC Source AXIS Transaction Monitor", adc_src_axis_agent);
+      dac_dst_axis_mon = new("DAC Destination AXIS Transaction Monitor", dac_dst_axis_agent);
+      adc_dst_axi_pt_mon = new("ADC Destination AXI Transaction Monitor", adc_dst_axi_pt_agent);
+      dac_src_axi_pt_mon = new("DAC Source AXI Transaction Monitor", dac_src_axi_pt_agent);
+
+      scoreboard_tx = new("Data Offload Verification Environment TX Scoreboard");
+      scoreboard_rx = new("Data Offload Verification Environment RX Scoreboard");
+
+    endfunction
+
+    //============================================================================
+    // Configure environment
+    //   - Configure the sequencer VIPs with an initial configuration before starting them
+    //============================================================================
+    task configure();
+
+      // ADC stub
+      adc_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR);
+      adc_src_axis_seq.set_keep_all();
+
+      // DAC stub
+      dac_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE);
+
+    endtask
+
+    //============================================================================
+    // Start environment
+    //   - Connect all the agents to the scoreboard
+    //   - Start the agents
+    //============================================================================
+    task start();
+
+      super.start();
+
+      adc_src_axis_agent.start_master();
+      dac_dst_axis_agent.start_slave();
+      adc_dst_axi_pt_agent.start_monitor();
+      dac_src_axi_pt_agent.start_monitor();
+
+      scoreboard_tx.set_source_stream(dac_src_axi_pt_mon);
+      scoreboard_tx.set_sink_stream(dac_dst_axis_mon);
+
+      scoreboard_rx.set_source_stream(adc_src_axis_mon);
+      scoreboard_rx.set_sink_stream(adc_dst_axi_pt_mon);
+
+    endtask
+
+    //============================================================================
+    // Start the test
+    //   - start the RX scoreboard and sequencer
+    //   - start the TX scoreboard and sequencer
+    //   - setup the RX DMA
+    //   - setup the TX DMA
+    //============================================================================
+    task test();
+
+      fork
+        adc_src_axis_seq.run();
+        dac_dst_axis_seq.run();
+
+        adc_src_axis_mon.run();
+        dac_dst_axis_mon.run();
+        adc_dst_axi_pt_mon.run();
+        dac_src_axi_pt_mon.run();
+
+        scoreboard_tx.run();
+        scoreboard_rx.run();
+      join_none
+
+    endtask
+
+
+    //============================================================================
+    // Post test subroutine
+    //============================================================================
+    task post_test();
+      // Evaluate the scoreboard's results
+    endtask
+
+    //============================================================================
+    // Run subroutine
+    //============================================================================
+    task run;
+
+      //pre_test();
+      test();
+
+    endtask
+
+    //============================================================================
+    // Stop subroutine
+    //============================================================================
+    task stop;
+
+      super.stop();
+
+      adc_src_axis_seq.stop();
+      adc_src_axis_agent.stop_master();
+      dac_dst_axis_agent.stop_slave();
+
+      post_test();
+
+    endtask
+
+  endclass
+
+endpackage