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Release Candidate v2.51.0 #1196

Merged
merged 26 commits into from
Oct 2, 2024
Merged

Release Candidate v2.51.0 #1196

merged 26 commits into from
Oct 2, 2024

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ruck314
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@ruck314 ruck314 commented Sep 23, 2024 •
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ruck314 and others added 23 commits September 20, 2024 14:06
@ruck314
adding userCLk to SelectioDeserUltraScale.vhd
5106757 
mapping CLKOUT1 to userClk, which is a useful optional clock reference
@ruck314
adding Pgp4RxLiteLowSpeed.vhd
498884a
@ruck314
Merge pull request #1194 from slaclab/ruckman/SelectioDeserUltraScale
9e5df72 
adding userCLk to SelectioDeserUltraScale.vhd
@hsandber
Increased range of SACI_NUM_CHIPS_G from 4 to 6.
572db27
@ruck314
Update RstSync.vhd
eddb613 
### Description
- Using "std_logic" instead of "sl" for generics due to issues with SystemVerilog handling VHDL subtype on generics properly
@ruck314
Merge pull request #1198 from slaclab/RstSync-std_logic
062d3b1 
Update RstSync.vhd
@ruck314
remove AXIL_CLK_FREQ_G default to force user to define it
e972e75
@ruck314
remove AXIL_CLK_FREQ_G default to force user to define it
c6b9e8b
@ruck314
Merge pull request #1195 from slaclab/Pgp4RxLiteLowSpeed
63d5f22 
adding Pgp4RxLiteLowSpeed.vhd
@ruck314
adding support to run SACI clock when asicRstL asserted in SACI_CLK_F…
1ed83db 
…REERUN_G=false mode
@ruck314
Merge pull request #1199 from slaclab/AxiLiteSaciMaster-asicRstL-aware
5008bb0 
Updates to AxiLiteSaciMaster.vhd & SaciMaster2.vhd
@ruck314
Pgp4RxLiteLowSpeedLane.vhd Update
75e91c1 
Mask off the Valid until the gearbox is locked
@ruck314
Merge pull request #1200 from slaclab/Pgp4RxLiteLowSpeedLane
ea63530 
Pgp4RxLiteLowSpeedLane.vhd Update
@ruck314
Removing upper bound from range
b429843
@ruck314
Merge pull request #1197 from slaclab/saci_6_chip
de4825d 
Increased range of SACI_NUM_CHIPS_G to support more than 4 chips
@ruck314
adding TxDisable to _Qsfp.py
3ea9a75
@ruck314
adding PowerOverride & PowerMode registers
56ad103
@cbakalis-slac
introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to pr…
2bff33d 
…epare for asic deployment
@cbakalis-slac
remove defaults on rst input ports; purge SIMULATION_G from Pgp4Rx.vhd
3c04de5
@ruck314
bug fix for existing builds
ba2710e
@ruck314
Merge pull request #1204 from slaclab/pgp4lite-rstPolarity
000e2e6 
introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment
@ruck314
restoring default on crcPwrOnRst after PR#1204
6d5bba6
@ruck314
restoring default on crcPwrOnRst after PR#1204
03e838e
@ruck314 ruck314 marked this pull request as ready for review October 2, 2024 17:39
cbakalis-slac
cbakalis-slac requested changes Oct 2, 2024
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@cbakalis-slac cbakalis-slac left a comment

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See comments. Some code justification needed.

Regarding the sl vs std_logic_vector: maybe we need to do this on a different branch since it is a lot of work needed?

@ruck314 ruck314 merged commit 266afd6 into main Oct 2, 2024
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@cbakalis-slac cbakalis-slac cbakalis-slac approved these changes

@bengineerd bengineerd Awaiting requested review from bengineerd

@king-pietro king-pietro Awaiting requested review from king-pietro

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3 participants
@ruck314 @cbakalis-slac @hsandber