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Release Candidate v2.51.0 #1196

Merged
merged 26 commits into from
Oct 2, 2024
Merged

Release Candidate v2.51.0 #1196

merged 26 commits into from
Oct 2, 2024

Commits on Sep 20, 2024

  1. adding userCLk to SelectioDeserUltraScale.vhd 

    mapping CLKOUT1 to userClk, which is a useful optional clock reference
    @ruck314
    ruck314 committed Sep 20, 2024
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Commits on Sep 23, 2024

  1. adding Pgp4RxLiteLowSpeed.vhd

    @ruck314
    ruck314 committed Sep 23, 2024
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  2. Merge pull request #1194 from slaclab/ruckman/SelectioDeserUltraScale 

    adding userCLk to SelectioDeserUltraScale.vhd
    @ruck314
    ruck314 authored Sep 23, 2024
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Commits on Sep 24, 2024

  1. Increased range of SACI_NUM_CHIPS_G from 4 to 6.

    @hsandber
    hsandber authored Sep 24, 2024
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Commits on Sep 25, 2024

  1. Update RstSync.vhd 

    ### Description
- Using "std_logic" instead of "sl" for generics due to issues with SystemVerilog handling VHDL subtype on generics properly
    @ruck314
    ruck314 authored Sep 25, 2024
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  2. Merge pull request #1198 from slaclab/RstSync-std_logic 

    Update RstSync.vhd
    @ruck314
    ruck314 authored Sep 25, 2024
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Commits on Sep 26, 2024

  1. remove AXIL_CLK_FREQ_G default to force user to define it

    @ruck314
    ruck314 authored Sep 26, 2024
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  2. remove AXIL_CLK_FREQ_G default to force user to define it

    @ruck314
    ruck314 authored Sep 26, 2024
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  3. Merge pull request #1195 from slaclab/Pgp4RxLiteLowSpeed 

    adding Pgp4RxLiteLowSpeed.vhd
    @ruck314
    ruck314 authored Sep 26, 2024
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  4. adding support to run SACI clock when asicRstL asserted in SACI_CLK_F… 

    …REERUN_G=false mode
    @ruck314
    ruck314 committed Sep 26, 2024
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Commits on Sep 27, 2024

  1. Merge pull request #1199 from slaclab/AxiLiteSaciMaster-asicRstL-aware 

    Updates to AxiLiteSaciMaster.vhd & SaciMaster2.vhd
    @ruck314
    ruck314 authored Sep 27, 2024
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Commits on Sep 28, 2024

  1. Pgp4RxLiteLowSpeedLane.vhd Update 

    Mask off the Valid until the gearbox is locked
    @ruck314
    ruck314 committed Sep 28, 2024
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Commits on Sep 30, 2024

  1. Merge pull request #1200 from slaclab/Pgp4RxLiteLowSpeedLane 

    Pgp4RxLiteLowSpeedLane.vhd Update
    @ruck314
    ruck314 authored Sep 30, 2024
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Commits on Oct 1, 2024

  1. Removing upper bound from range

    @ruck314
    ruck314 authored Oct 1, 2024
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  2. Merge pull request #1197 from slaclab/saci_6_chip 

    Increased range of SACI_NUM_CHIPS_G to support more than 4 chips
    @ruck314
    ruck314 authored Oct 1, 2024
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  3. adding TxDisable to _Qsfp.py

    @ruck314
    ruck314 committed Oct 1, 2024
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  4. adding PowerOverride & PowerMode registers

    @ruck314
    ruck314 committed Oct 1, 2024
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  5. introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to pr… 

    …epare for asic deployment
    @cbakalis-slac
    cbakalis-slac committed Oct 1, 2024
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  6. remove defaults on rst input ports; purge SIMULATION_G from Pgp4Rx.vhd

    @cbakalis-slac
    cbakalis-slac committed Oct 1, 2024
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Commits on Oct 2, 2024

  1. bug fix for existing builds

    @ruck314
    ruck314 authored Oct 2, 2024
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  2. Merge pull request #1204 from slaclab/pgp4lite-rstPolarity 

    introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment
    @ruck314
    ruck314 authored Oct 2, 2024
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  3. restoring default on crcPwrOnRst after PR#1204

    @ruck314
    ruck314 authored Oct 2, 2024
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  4. restoring default on crcPwrOnRst after PR#1204

    @ruck314
    ruck314 authored Oct 2, 2024
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  5. Fixed typo

    @ruck314
    ruck314 authored Oct 2, 2024
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  6. Merge pull request #1203 from slaclab/Qsfp-TxDisable 

    _Qsfp.py Update
    @ruck314
    ruck314 authored Oct 2, 2024
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  7. ./emacs -f vhdl-beautify-buffer -f vhdl-update-sensitivity-list-buffe… 

    …r -f save-buffer
    @ruck314
    ruck314 committed Oct 2, 2024
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