Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.

Convolutional accelerator kernel, target ASIC & FPGA

A FPGA Based CNN accelerator, following Google's TPU V1.

hardware design of universal NPU(CNN accelerator) for various convolution neural network

A DNN Accelerator implemented with RTL.

Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.

Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.

Modified version of the "Explore the energy-efficient dataflow scheduling for neural networks. "

2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition

基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植

A CNN processor that takes layers of CNN as input instruction and performs the respective operation.

This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model architecture.

Design of CNN Accelerator Using DE1-SoC Board