Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
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Updated
Dec 15, 2024 - VHDL
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Using Nim to interface with SystemVerilog test benches via DPI-C
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
First Step in UVM
Basic APB-compatible module designed for use with Verilator, but should work with any DPI-C compatible simulator.
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