openlane-flow

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Here are 14 public repositories matching this topic...

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

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Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

asic vlsi vlsi-physical-design rtl2gds openlane sky130 openlane-flow

Updated Sep 17, 2022

ShonTaware / OpenSource_Physical_Design

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This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

open-source vlsi-physical-design sky130 openlane-flow

Updated Feb 22, 2022

harshithsn / Universal-Shift-Register

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This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

vlsi vlsi-physical-design openlane universal-shift-register openlane-flow

Updated Jul 19, 2022
Verilog

CodePurble / sap

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The SAP-1 in Verilog, and now as an ASIC!

asic verilog openlane-flow sap-computers

Updated Nov 5, 2022
Verilog

krutideepanpanda / RISC-V-based-micro-controller-using-OpenLane

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This is part of EC383 - Mini Project in VLSI Design.

verilog vlsi verilog-project vlsi-design openlane verilog-processor openlane-flow

Updated May 8, 2022
Verilog

MayurTA / VSD-IAT_workshop

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Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry

vsd vlsi vlsi-cad openlane gdsii-flow openlane-flow

Updated Feb 25, 2021

ShyamRazesh / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

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2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

open-source vlsi-physical-design sky130 openlane-flow

Updated Apr 17, 2024

SKpro-glitch / RISCV-Processor-ASIC

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This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

open-source processor-architecture asic fpga verilog hardware-designs vlsi verilog-hdl risc-v riscv32 asic-verification processor-design vlsi-design asic-design openlane openlane-flow

Updated Nov 15, 2024
Verilog

Pa1mantri / VSDMemSOC

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VSDMemSOC Implementation flow:: RTL2GDSII

macros riscv yosys gdsii physical-design openroad opensta openlane-flow sram-macro

Updated Mar 1, 2024
Verilog

arhamhashmi01 / openlane-verification

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This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.