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Machine learning on FPGAs using HLS

Send video/audio over HDMI on an FPGA

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Documenting the Xilinx 7-series bit-stream format.

An abstraction library for interfacing EDA tools

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Notes on the Red Pitaya Open Source Instrument

Installs Vivado on M1/M2/M3 macs

FPGA Accelerator for CNN using Vivado HLS

HDL support for VS Code

Build Customized FPGA Implementations for Vivado

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Image Processing Toolbox in Verilog using Basys3 FPGA

车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

Verilog Implementation of an ARM LEGv8 CPU