GitHub - vmazashvili/Mealy-FSM: simple Mealy FSM done in verilog for Altera Cylcone V GX Starter kit. the code is written using three always statements. verilog file containing code with two always block is also included

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simple Mealy FSM done in verilog for Altera Cylcone V GX Starter kit. the code is written using three always statements. verilog file containing code with two always block is also included

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Xilinx ISe synthesis docs		Xilinx ISe synthesis docs
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
.gitignore		.gitignore
FSM.qpf		FSM.qpf
FSM.qsf		FSM.qsf
FSM.qws		FSM.qws
FSM_assignment_defaults.qdf		FSM_assignment_defaults.qdf
FSM_nativelink_simulation.rpt		FSM_nativelink_simulation.rpt
FSM_tb.v		FSM_tb.v
FSM_tb.v.bak		FSM_tb.v.bak
baseline_c5gx.v		baseline_c5gx.v
baseline_c5gx.v.bak		baseline_c5gx.v.bak
c5_pin_model_dump.txt		c5_pin_model_dump.txt
qar_info.json		qar_info.json

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simple Mealy FSM done in verilog for Altera Cylcone V GX Starter kit. the code is written using three always statements. verilog file containing code with two always block is also included

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