Fixes for building nRF5340 for both application and network cores. Re…

…vert some "CORE" logic, easier to have different targets.

.github/workflows/test-configs.yml

@@ -116,12 +116,18 @@ jobs:
       arch: arm
       config-file: ./config/examples/nrf52840.config
 
-  nrf5340_test:
+  nrf5340_app_test:
     uses: ./.github/workflows/test-build.yml
     with:
       arch: arm
       config-file: ./config/examples/nrf5340.config
 
+  nrf5340_net_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/nrf5340_net.config
+
   nxp_p1021_test:
     uses: ./.github/workflows/test-build.yml
     with:

config/examples/nrf5340.config

@@ -43,3 +43,7 @@ WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x200000
 V?=0
 DEBUG?=0
 DEBUG_UART?=1
+USE_GCC=1
+
+CFLAGS_EXTRA+=-DDEBUG_FLASH
+

config/examples/nrf5340_net.config

@@ -0,0 +1,49 @@
+ARCH?=ARM
+TZEN?=0
+TARGET?=nrf5340_net
+SIGN?=ECC256
+HASH?=SHA256
+WOLFBOOT_VERSION?=1
+VTOR?=1
+CORTEX_M0?=0
+CORTEX_M33?=1
+NO_ASM?=0
+NO_MPU=1
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=0
+
+SPMATH?=1
+RAM_CODE?=1
+
+DUALBANK_SWAP?=0
+FLAGS_HOME=0
+DISABLE_BACKUP=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+QSPI_FLASH?=0
+
+# Flash base for network core
+ARCH_FLASH_OFFSET=0x01000000
+
+# Flash is 4KB pages (app) 2KB pages (net)
+WOLFBOOT_SECTOR_SIZE?=0x1000
+
+# Application Partition Size (256KB-64KB)
+WOLFBOOT_PARTITION_SIZE?=0x18000
+
+# Reserve 64KB for wolfBoot
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x01010000
+
+# Flash offset for update (not used)
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0
+
+# Flash offset for swap (not used)
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0
+
+V?=0
+DEBUG?=0
+DEBUG_UART?=1
+USE_GCC=1
+
+CFLAGS_EXTRA+=-DDEBUG_FLASH
+

docs/Targets.md

@@ -2133,23 +2133,49 @@ Tested with the Nordic nRF5340-DK. This device has two cores:
 
 The cores communicate using the IPC peripheral.
 
-### Building Nordic nRF5340
+The network core can access application core resources (flash, RAM, and peripherals) when granted permission through the application's DCNF and SPU settings. A small portion of the application core RAM is dedicated to the exchange of messages between the application and network cores.
 
-Setup the configuration to build: `cp config/examples/nrf5340.config .config`
+### Building / Flashing Nordic nRF5340
 
-Build application core loading using: `make clean && make`
-Build network core loader using: `make CORE=2`
+#### Application Core
 
-Flashing with JLink:
+Flash base: 0x00000000, SRAM base: 0x20000000
+
+Building Application core:
+
+```sh
+cp config/examples/nrf5340.config .config
+make clean
+make
+```
+
+Flashing Application core with JLink:
 
 ```
 JLinkExe -device nRF5340_xxAA_APP -if SWD -speed 4000 -jtagconf -1,-1 -autoconnect 1
-erase
 loadbin factory.bin 0x0
 rnh
 ```
 
-Note: For network core use: `-device nRF5340_xxAA_NET`
+#### Network Core
+
+Flash base: 0x01000000, SRAM base: 0x21000000
+
+Building Network core:
+
+```sh
+cp config/examples/nrf5340_net.config .config
+make clean
+make
+```
+
+Flashing Network core with JLink:
+
+```
+JLinkExe -device nRF5340_xxAA_NET -if SWD -speed 4000 -jtagconf -1,-1 -autoconnect 1
+loadbin factory.bin 0x01000000
+rnh
+```
 
 ### Debugging Nordic nRF5340
 

hal/nrf5340.c

@@ -1,6 +1,6 @@
-/* nrf52.c
+/* nrf5340.c
  *
- * Copyright (C) 2021 wolfSSL Inc.
+ * Copyright (C) 2024 wolfSSL Inc.
  *
  * This file is part of wolfBoot.
  *
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  */
 
+/* Note: Also used by TARGET_nrf5340_net */
 #ifdef TARGET_nrf5340
 
 #include <stdint.h>
@@ -28,6 +29,14 @@
 #include "printf.h"
 #include "nrf5340.h"
 
+/* TODO:
+ * Key Storage: See 7.1.18.4.2 Key storage:
+ * The key storage region of the UICR can contain multiple keys of different type, including symmetrical keys, hashes, public/private key pairs and other device secrets
+ * Key headers are allocated an address range of 0x400 in the UICR memory map, allowing a total of 128 keys to be addressable inside the key storage region.
+ * The key storage region contains multiple key slots, where each slot consists of a key header and an associated key value. The key value is limited to 128 bits.
+ * Any key size greater than 128 bits must be divided and distributed over multiple key slot instances.
+ */
+
 #ifdef TEST_FLASH
 static int test_flash(void);
 #endif
@@ -40,7 +49,10 @@ static int test_flash(void);
 
 void uart_init(void)
 {
-    /* nRF5340-DK UART0=P1.01, UART1=P0.20 */
+    /* nRF5340-DK:
+     * App: UART0=P1.01, UART1=P0.20
+     * Net: UART0= */
+
     UART_ENABLE(UART_SEL) = 0;
 #if UART_SEL == 0
     GPIO_PIN_CNF(1, 1) = GPIO_CNF_OUT;
@@ -181,12 +193,18 @@ static void clock_init(void)
     while (CLOCK_HFCLKSTARTED == 0);
 }
 
-/* CPU is running at 128MHz so 128 NOP's = 1us */
 void sleep_us(unsigned int us)
 {
-    unsigned int nop_us = (CPU_CLOCK / 1000000);
-    us *= nop_us;
-    while (us-- > 0) {
+    /* Calculate ops per us (128MHz=128 instructions per 1us */
+    unsigned long nop_us = (CPU_CLOCK / 10000000);
+    nop_us *= us;
+    /* instruction for each iteration */
+#ifdef DEBUG
+    nop_us /= 5;
+#else
+    nop_us /= 2;
+#endif
+    while (nop_us-- > 0) {
         NOP();
     }
 }

hal/nrf5340.h

@@ -24,18 +24,18 @@
 
 /* Build-time gate for secure or non-secure peripherals.
  * At boot-time peripherals are secure */
-#if defined(CORE) && CORE == 2
-    #define TARGET_nrf5340_NET /* core 2 */
-
+#ifdef TARGET_nrf5340_net
+    /* Network core */
     #undef QSPI_FLASH /* not supported on network core */
 #else
-    #define TARGET_nrf5340_APP /* core 1 */
+    /* Application core */
     #ifndef TZEN
+        /* at reset/power on wolfBoot is using secure bases */
         #define TZEN
     #endif
 #endif
 
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
 #define CPU_CLOCK 128000000UL /* 128MHz */
 #else
 #define CPU_CLOCK  64000000UL /*  64MHz */
@@ -44,15 +44,60 @@
 
 /* Assembly helpers */
 #define DMB() __asm__ volatile ("dmb")
+#define DSB() __asm__ volatile ("dsb")
+#define ISB() __asm__ volatile ("isb")
 #define NOP() __asm__ volatile ("nop")
 
 void sleep_us(unsigned int us);
 
 /* PSEL Port (bit 5) - Used for various PSEL (UART,SPI,QSPI,I2C,NFC) */
 #define PSEL_PORT(n)         (((n) & 0x1) << 5)
 
+/* Domain Configuration */
+#ifdef TARGET_nrf5340
+    #ifdef TZEN
+        #define DCNF_BASE (0x50000000)
+    #else
+        #define DCNF_BASE (0x40000000)
+    #endif
+#else
+    #define DCNF_BASE     (0x41000000)
+#endif
+
+#define DCNF_CPUID         *((volatile uint32_t *)(DCNF_BASE + 0x420))
+#ifdef TARGET_nrf5340
+    /* allows blocking of network cores ability to resources on application core */
+    #define DCNF_EXTPERI0_PROT *((volatile uint32_t *)(DCNF_BASE + 0x440))
+    #define DCNF_EXTRAM0_PROT  *((volatile uint32_t *)(DCNF_BASE + 0x460)) /* Eight 64KB slaves bit 0=0x20000000-0x20010000 (64KB) */
+    #define DCNF_EXTCODE0_PROT *((volatile uint32_t *)(DCNF_BASE + 0x480))
+#endif
+
+/* OTP */
+#define UICR_BASE (0x00FF8000UL)
+
+/* Reset */
+#ifdef TARGET_nrf5340
+    #ifdef TZEN
+        #define RESET_BASE (0x50005000)
+    #else
+        #define RESET_BASE (0x40005000)
+    #endif
+#else
+    #define RESET_BASE     (0x41005000)
+#endif
+#define NETWORK_RESETREAS *((volatile uint32_t *)(RESET_BASE + 0x400))
+#define NETWORK_RESETREAS_RESETPIN  (1 << 0)
+#define NETWORK_RESETREAS_DOG0      (1 << 1) /* watchdog timer 0 */
+#define NETWORK_RESETREAS_SREQ      (1 << 3) /* soft reset */
+#define NETWORK_RESETREAS_OFF       (1 << 5) /* wake from off */
+#define NETWORK_RESETREAS_MFORCEOFF (1 << 23)
+#define NETWORK_FORCEOFF  *((volatile uint32_t *)(RESET_BASE + 0x614))
+#define NETWORK_FORCEOFF_RELEASE 0
+#define NETWORK_FORCEOFF_HOLD    1
+
+
 /* Non-volatile memory controller */
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
     #ifdef TZEN
         #define NVMC_BASE (0x50039000)
     #else
@@ -78,7 +123,7 @@ void sleep_us(unsigned int us);
 #define FLASH_PAGE_SIZE (4096)
 
 /* Clock control */
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
     #ifdef TZEN
         #define CLOCK_BASE  (0x50005000)
     #else
@@ -109,7 +154,7 @@ void sleep_us(unsigned int us);
 
 
 /* GPIO Port (0-1) */
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
     #ifdef TZEN
         #define GPIO_BASE(n) (0x50842500 + (((n) & 0x1) * 0x300))
     #else
@@ -137,14 +182,14 @@ void sleep_us(unsigned int us);
 #define GPIO_CNF_MCUSEL(n)   (((n) & 0x7) << 28)
 
 /* UART (0-1) */
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
     #ifdef TZEN
         #define UART_BASE(n) (0x50008000 + (((n) & 0x1) * 0x1000))
     #else
         #define UART_BASE(n) (0x40008000 + (((n) & 0x1) * 0x1000))
     #endif
 #else
-    #define UART_BASE(n)     (0x41013000) /* only UARTE0 */
+    #define UART_BASE(n)     (0x41013000) /* UARTE0 only */
 
 #endif
 #define UART_TASK_STARTTX(n) *((volatile uint32_t *)(UART_BASE(n) + 0x008))
@@ -163,7 +208,7 @@ void sleep_us(unsigned int us);
 void uart_write_sz(const char* c, unsigned int sz);
 
 /* SPI (0-2) */
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
     #ifdef TZEN
         #define SPI_BASE(n)  (0x50008000 + (((n) & 0x3) * 0x1000))
     #else
@@ -200,7 +245,7 @@ void uart_write_sz(const char* c, unsigned int sz);
 #define SPI_FREQ_M32  0x14000000
 
 /* QSPI */
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
     #ifdef TZEN
         #define QSPI_BASE         (0x5002B000)
     #else
@@ -276,10 +321,13 @@ void uart_write_sz(const char* c, unsigned int sz);
     #define QSPI_CINSTRCONF_WREN           (1 << 15) /* send WREN opcode 0x6 before */
 
     #define QSPI_IFTIMING_RXDELAY(n)       (((n) & 0x7) << 8)
+#else
+    /* Disable QSPI Flash */
+    #undef QSPI_FLASH
 #endif
 
 /* interprocessor communication (IPC) peripheral */
-#ifdef TARGET_nrf5340_APP
+#ifdef TARGET_nrf5340
     #ifdef TZEN
     #define IPC_BASE      (0x5002A000)
     #else

hal/nrf5340.ld

@@ -1,7 +1,8 @@
 MEMORY
 {
-    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
-    RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 64K
+    FLASH (rx) :     ORIGIN = @ARCH_FLASH_OFFSET@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
+    FLASH_NET (rx) : ORIGIN = 0x01000000, LENGTH = 256K
+    RAM (rwx) :      ORIGIN = 0x20000000, LENGTH = 64K
 }
 
 SECTIONS

hal/nrf5340_net.c

@@ -0,0 +1,28 @@
+/* nrf5340_net.c
+ *
+ * Copyright (C) 2024 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#ifdef TARGET_nrf5340_net
+
+/* use code from nrf5340.c */
+#define TARGET_nrf5340
+#include "nrf5340.c"
+
+#endif /* TARGET_* */