Releases: xver/Shunt
Python to System Verilog integration
What’s new?
- System Verilog - Python* integration :
Updates:
• docs , debug print out, .gitignore , run_debug, minor cosmetic updates
Regression mode support: Simultaneous allocation of TCP/IP ports.
Support for regression mode: multiple server/client simultaneous assignment of TCP/IP ports. (Examples, doc updates) + minor updates
Dynamic port allocation (DPA) mode:
Functions:
shunt_cs_init_initiator
shunt_cs_tcp_parent_init_initiator_dpa
shunt_cs_init_target
shunt_cs_tcp_parent_init_initiator_dpa
Global defines:
SHUNT_DEFAULT_TCP_PORT
###Collision resolution of the occupied TCP/IP port
Function build in support:
shunt_prim_tcp_parent_init_initiator
Global defines:
SHUNT_DEFAULT_COLLISION_ATTEMPT_LIMIT
SHUNT_DEFAULT_COLLISION_LOW
SHUNT_DEFAULT_COLLISION_UP
cumulative updates
What’s new?
• c++ namespaces no extern "C"
Updates:
• docs , debug print out, .gitignore , run_debug, minor cosmetic updates
ARM AXI bus
What’s new?
• ARM AXI bus (Advanced eXtensible Interface) support over TCP/IP (new data structures, functions, examples)
• Predefined hash functions
• VCS DPI header file
• Shunt “no dpi” target /home/v/workspace/Shunt/bin/libCutils.so
• New data type shunt_long_t (default is "long long")
Bug fixes:
• Bad header (shunt_dpi_tlm_recv_gp_data)
• Long data payload failures
cleanup and SystemC related fixes
Cumulative release: cleanup & SystemC related fixes
SystemC compile/link cleanup
cleanup : tab & trailing whitespaces, c++ compile/link -Wall -Werror -Wpedantic -Wextra -Wno-odr
System Verilog TLM-2.0 generic payload over TCP/IP
add System Verilog TLM-2.0 over TCP utils and example + error fixes + docs
SystemC TLM-2.0 over TCP/IP
add SystemC TLM-2.0 over TCP utils and example + error fixes.
Fixed size packet communication
TCP/IP optimization ,
new fixed size packet communication functions,
big/little endian support.
examples and doc updates
Accumulated fixes
verilator 4.020 support and various accumulated fixes