Python to System Verilog integration

What’s new?

• System Verilog - Python* integration :

• utils: https://github.com/xver/Shunt/tree/master/utils/py/shunt_py
• examples: https://github.com/xver/Shunt/tree/master/examples/py/sv2py

Updates:
• docs , debug print out, .gitignore , run_debug, minor cosmetic updates