A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
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Updated
Jul 15, 2016 - Tcl
A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
Gate-Level Simulation on a GPU
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
Game using touch screen implemented to FPGA.
PYNQ DMA benchmark project
Ansible role for installation of Xilinx Vivado on Ubuntu
64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs
Tools for automating the Vivado project partial reconfiguration flow
SPI ELF bootloader for Xilinx Microblaze processors
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
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