This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
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Updated
May 4, 2024 - SystemVerilog
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
Practice Codes of SystemVerilog Language
A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board
Includes lab exercises from my Computer Organization and Digital Design module. It features implementations of various components inside a processor using VHDL . Finally I make 4 bit nanoprocessor combining all components those build in previous labs.
I am trying to develop my skills through daily practice and consistency.
Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation
Circuit design fundamentals - a 3rd year banchelor CS course in ITMO University
Example of Python and PyTest powered workflow for a HDL simulation
Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
Repurposing existing HDL tools to help writing better code
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